AD9213 Bring Up

Hi Experts:

I tried to bring up AD9213 with the ADS-V1EBZ to acquire the baseband data.
I followed the quick start guide on ADI wiki.

My settings and steps were following it.

https://wiki.analog.com/ad9213

 I used a typical LVDS REF 625MHz and 10GHz sampling clock.

The TMU is working normally, showing temperature dynamically.

The PLL locked/valid LED are also green light in ACE tool.

But after I followed step 21.C click Run Once, nothing showed up in the time domain view or FFT.

The tool then hung up for several minutes.

 

I updated JESD link status and the button turns red in GT RXRESETDONE Error/CGS Error/ILAS Error.

I tried disable ACE -> turn off the board for multiple times, but still cannot get data from the “Proceed to analysis” tab.

I tried the steps below, the TP5 seems to be alright.

I also updated ACE to the latest version and restart computer.

  • If after repeated attempts the ACE startup procedure is not successful:
    • Check that the jumpers are placed on the AD9213/9217 evaluation board as shown in step 4.
    • Check that all signal generators are on and at the correct frequencies and power levels. (EXTCLK LVDS 1.43VDC)
    • Check that 3.3V appears at TP5 on the Regulator Board. (measured 3.25V)

 

Or is there any suggestions for debug?

Is there DC test mode or default SYSREF source that I can use on ADS8-V1EBZ eval board?

Thanks!

  • 0
    •  Analog Employees 
    on Apr 22, 2021 1:50 PM

    Hi Brant,

    Thank you for your interest in AD9213.

    Are the sample clock and FPGA reference clock signal generators synchronized with each other?

    Thank you.

    Doug

  • Hi Doug:

    Thanks for your advice, I synchronized FPGA reference (625MHz = 4*156.25MHz) and signal generator (10,000 = 64*156.25MHz) with the same 156.25MHz clock source.

    There is only two error left in CGS Error and ILAS Error. Got no “RXRESETDONE” error.

    I think there might be some JESD link establishment between FPGA and AD9213.

    The description of the flow of CGS phase is brief:

    1. JESD Rx(ADS8-V1EBZ) send sync request from SYNCINB_x pin to JESD Tx(AD9213) by asserting (pull low)
    2. JESD Tx begins to transmit K28.5
    3. JESD Rx PHY CDR locked and sliced symbol
    4. JESD Rx wait for at least 4 consecutive symbols
    5. JESD Rx deassert SNYCINB_X (pull high)
    6. JESD Tx Rx PCS link, transmit ILAS

    Here are some questions need your advice:

    1. Is there any log we could dump through ACE tool to check which step of CGS failed? I tried forcing register 0x508, but nothing happened.

    2. Can I measure the SYNCINB_x pin from the board? (both Tx and Rx side)?

    3. Can I force JESD Tx to send direct clock output to check the frequency and jitter of JESD stream?

  • 0
    •  Analog Employees 
    on May 3, 2021 8:12 PM in reply to brantchen

    Can you please check to see if the ADS8-v1 is connected to a valid USB3.0 port on your PC, and that you are using the supplied USB3.0 cable to connect the FPGA board to the PC? Just thinking outside the box for a moment here. from the errors, it seems the AD9213's JESD204B PLL is locked, which means it is happy. the FPGA is not flagging a REFCLK error which means it is happy. 

    If the problem persists, i would recommend a scrub uninstall of ACE (with SDPDrivers and LRFDrivers removed) and reinstall of ACE. Repeat the steps.