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trouble shooting AD9675 JESD204B data read zero for intermittent

1.Main IC: XC7A100T(FPGA) + AD9675
2.Refclk: buffer IC drive the same 125MHz clock to both ADC & FPGA(GTP refclk)
    clock in 125MHz
    enable RF decimator

4.Parameter setting is same with the IP core.

Address Data
0x142 0x01
0x000 0x3C
0x002 0x30
0x0FF 0x01
0x004 0x0F
0x005 0x3F
0x113 0x04
0x011 0x86
0xF00 0xFF
0xF01 0x7F
0xF02 0x00
0xF03 0x08
0xF04 0x08
0x10C 0x00
0x014 0x01
0x008 0x00
0x021 0x12
0x199 0x80
0x143 0x00
0x188 0x01
0x18B 0x27
0x18C 0x72
0x150 0x03
0x182 0x82
0x181 0x02
0x152 0x07 K=8
0x154 0x0F N=16
0x186 0xAA
0x142 0x14
0x10C 0x20
0x00F 0xB0
0x02B 0x43

5.Format of data:
    data| 0 |data| 0 | data| 0 |data| 0 | data| 0 |data| 0 | ...