AD6641 Trigger fill of FIFO using FILL+- Pins

Dear ADI-Team, 

I am controlling the ADC via SPI. Fill, Dump, readout, configuration settings etc. works like a charm. 

However, now I want to initate a fill using the FILL+- pins which does not yet work (FIFO status remains emtpy, does not fill). I think I do not understand the datasheet and therefore I would be glad if someone "fills" me in ;) 

  • What signal does the ADC expect at the FILL+ and FILL- pins which provokes a filling of the FIFO? What signal at the FILL+ and FILL- pin do I need to apply to trigger a fill?

According to the datasheet "[...] the user initiates a capture by driving the FILL+- pins high [...]" or by "[...] asserting the differential FILL+- pins [...]". And that is the part I do not understand. Since FILL+ and FILL- are complementary pins, does the ADC expect FILL+ = +1.8 V and FILL- = -1.8 V? Or should both pins be driven logic high that is FILL+ = +1.8 V, FILL- = +1.8 V? 

  • What about the timing? Should both pins the pulled high or low simultaneously? Or one after another? If the latter, are there any timing requirements I need to meet?

My sequence is the following:

  1. Power up ADC.
  2. Perform a soft reset.
  3. Put the ADC in single capture mode by writing the FIFO fill mode bits in the fill control register (0x101, 0).
  4. Trigger fill using FILL+- pins by pulling both FILL+ and FILL- to +1.8 V. (that where I am stuck, FIFO does not fill!)

Thank you in advance for your help. 

Simon



fixed typo
[edited by: SB235 at 10:41 AM (GMT -5) on 3 Feb 2021]
Parents
  • 0
    •  Analog Employees 
    on Feb 4, 2021 3:47 PM 2 months ago

    Hi, 

    The FILL+/- pins are a differential input, with a common mode of 0.9V. For FILL+/- to be HIGH, FILL+ should be 1.8V, and FILL- should be ground. They do not need to reach the full supply and ground levels, a difference of at least 0.2V will suffice.  In the single capture mode, once FILL+/-  HIGH is captured by a rising edge of the clock, then it must return to LOW to initiate the fill.  

    Regards, 

    David

  • Thank you David. I will try this next week and keep you updated.

    Just for clarification: By "rising edge of the clock" you mean the 500 MHz reference clock input? This has nothing to do with the SPI clock, correct? 

    Regarding the following plot, taken from here

    Is there a specific maximum FILL hold time requirement I should meet? Right now, I trigger the FILL ports by applying at the FILL+ 1.8 V for a short amount of time (by manually turning a power supply on and off) and then apply FILL+ to ground again. In general, this should trigger a fill, am I right?

    Have a nice weekend!

    Simon

  • 0
    •  Analog Employees 
    on Feb 8, 2021 2:22 PM 2 months ago in reply to SB235

    Hi, There is not a min / max specification, but if you are doing this manually, then it would surely get captured by multiple CLK periods.  However, you need to drive FILL- as well.  And this is not the SPI clock, it is CLK, then main converter clock.

    Regards, 

    David

  • Hi David,

    thank you. I'm still still struggling to issue a fill of the ADC using the FILL +/- pins.

    Just to be clear, the following procedure should lead to a fill or am I missing something?

    1. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V.
    2. Soft reset ADC.
    3. Put the ADC in single capture mode by writing the FIFO fill mode bits in the fill control register (0x101, 0).

    Here is the complete ADC configuration read out via SPI:

    : ------------------------------------------
    : ADC #4 - 0x00 Chip port config: 24
    : ADC #4 - 0x01 Chip ID: 160
    : ADC #4 - 0xFF Chip device update: 0
    : ADC #4 - 0x08 Modes: 0
    : ADC #4 - 0x14 Output mode: 8
    : ADC #4 - 0x101 Fill control: 0
    : ADC #4 - 0x102 FIFO config: 0
    : ADC #4 - 0x104 FIFO fill count: 127
    : ADC #4 - 0x105 FIFO settle count0: 0
    : ADC #4 - 0x106 FIFO settle count1: 0
    : ADC #4 - 0x107 Dump control: 1
    : ADC #4 - 0x10A FIFO status: 0
    : ------------------------------------------

    4. Apply at FILL+ pin +1.8 V. Apply at FILL- pin GND.
    5. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V.

    At this point, the FIFO should start being filled?

    Thank you.

    Regards,
    Simon

  • +1
    •  Analog Employees 
    on Feb 9, 2021 8:23 PM 2 months ago in reply to SB235

    Hi, 

    I need to clarify the FILL+/- .  This is a differential input, meaning that the logic state received by the device is (Fill+ (V)) - (Fill-(V).  So for logic HIGH, we want Fill+=1.8V, and FILL-=0V.  This gives (Fill+ (V)) - (Fill-(V)= 1.8 - 0 = 1.8V.  And for logic LOW, we want Fill+=0V, and FILL-=1.8V.  This gives (Fill+ (V)) - (Fill-(V)= 0 - 1.8 = -1.8V, which is logice LOW.  Note that in both states, the FILL+/- pins are within the supply rails of 0V (Ground) and 1.8V (AVDD).  

    Please see my comments below in Italic: 

    1. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V.  FILL- should be at +1.8V (see above)
    2. Soft reset ADC.
    3. Put the ADC in single capture mode by writing the FIFO fill mode bits in the fill control register (0x101, 0).

    Here is the complete ADC configuration read out via SPI:

    : ------------------------------------------
    : ADC #4 - 0x00 Chip port config: 24
    : ADC #4 - 0x01 Chip ID: 160 This should read back 0xA0
    : ADC #4 - 0xFF Chip device update: 0
    : ADC #4 - 0x08 Modes: 0
    : ADC #4 - 0x14 Output mode: 8
    : ADC #4 - 0x101 Fill control: 0
    : ADC #4 - 0x102 FIFO config: 0
    : ADC #4 - 0x104 FIFO fill count: 127
    : ADC #4 - 0x105 FIFO settle count0: 0
    : ADC #4 - 0x106 FIFO settle count1: 0
    : ADC #4 - 0x107 Dump control: 1
    : ADC #4 - 0x10A FIFO status: 0 This should read back 0x01 when a fill is complete
    : ------------------------------------------

    4. Apply at FILL+ pin +1.8 V. Apply at FILL- pin GND.
    5. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V. FILL- should be at +1.8V (see above)

    At this point, the FIFO should start being filled? I believe so

    I think the issue is the FILL- voltage as discussed above.  Taking Fill- outside the absolute max range (<-0.3V) may have damaged the device, but my experience is that they are pretty forgiving.  I do not think that the evaluation board is available from production (this is a fairly old device), so I'm guessing you are testing in your own system design.  Is that correct? 

    Regards, 

    David

Reply
  • +1
    •  Analog Employees 
    on Feb 9, 2021 8:23 PM 2 months ago in reply to SB235

    Hi, 

    I need to clarify the FILL+/- .  This is a differential input, meaning that the logic state received by the device is (Fill+ (V)) - (Fill-(V).  So for logic HIGH, we want Fill+=1.8V, and FILL-=0V.  This gives (Fill+ (V)) - (Fill-(V)= 1.8 - 0 = 1.8V.  And for logic LOW, we want Fill+=0V, and FILL-=1.8V.  This gives (Fill+ (V)) - (Fill-(V)= 0 - 1.8 = -1.8V, which is logice LOW.  Note that in both states, the FILL+/- pins are within the supply rails of 0V (Ground) and 1.8V (AVDD).  

    Please see my comments below in Italic: 

    1. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V.  FILL- should be at +1.8V (see above)
    2. Soft reset ADC.
    3. Put the ADC in single capture mode by writing the FIFO fill mode bits in the fill control register (0x101, 0).

    Here is the complete ADC configuration read out via SPI:

    : ------------------------------------------
    : ADC #4 - 0x00 Chip port config: 24
    : ADC #4 - 0x01 Chip ID: 160 This should read back 0xA0
    : ADC #4 - 0xFF Chip device update: 0
    : ADC #4 - 0x08 Modes: 0
    : ADC #4 - 0x14 Output mode: 8
    : ADC #4 - 0x101 Fill control: 0
    : ADC #4 - 0x102 FIFO config: 0
    : ADC #4 - 0x104 FIFO fill count: 127
    : ADC #4 - 0x105 FIFO settle count0: 0
    : ADC #4 - 0x106 FIFO settle count1: 0
    : ADC #4 - 0x107 Dump control: 1
    : ADC #4 - 0x10A FIFO status: 0 This should read back 0x01 when a fill is complete
    : ------------------------------------------

    4. Apply at FILL+ pin +1.8 V. Apply at FILL- pin GND.
    5. Apply at FILL+ pin GND. Apply at FILL- pin -1.8 V. FILL- should be at +1.8V (see above)

    At this point, the FIFO should start being filled? I believe so

    I think the issue is the FILL- voltage as discussed above.  Taking Fill- outside the absolute max range (<-0.3V) may have damaged the device, but my experience is that they are pretty forgiving.  I do not think that the evaluation board is available from production (this is a fairly old device), so I'm guessing you are testing in your own system design.  Is that correct? 

    Regards, 

    David

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