Excuse my non-perfect technical understanding, however;
We have a small device that implements the AD9246. The outputs are configured to 3.3V level and it runs at 80MHz. The outputs are connected directly to the FPGA input pins, the maximum distance of the tracks is approximately 10-15mm pin-to-pin and they all run side by side on the top layer. The second layer is solid GND and we have some GND vias under the ADC.
We are currently doing RF emissions testing on our product and it has failed because of excessive noise in all harmonics of 80MHZ. Some investigation has shown that the ADC output pin area is polluting the board and radiating 80MHZ harmonics through the connected sensor leads.
Reading another user's questions about maximum capacitive load, and the EVAL datasheet, I am asking;
-What can we do to minimise the noise?
-Would placing 22OHM resistors on as per the EVAL board give a noticeable/substantial reduction in noise (Or other value based on calculations for our specific implementation)?
-Is there something else that we should be doing (aside from good/normal PCB layout practises) that we should/could be doing?
Thanks kindly in advance for your helpful reply!
[edited by: Disco Inc. at 1:32 PM (GMT -5) on 3 Jan 2021]