AD9246 Output Noise

Hello,

Excuse my non-perfect technical understanding, however;

We have a small device that implements the AD9246. The outputs are configured to 3.3V level and it runs at 80MHz. The outputs are connected directly to the FPGA input pins, the maximum distance of the tracks is approximately 10-15mm pin-to-pin and they all run side by side on the top layer. The second layer is solid GND and we have some GND vias under the ADC.

We are currently doing RF emissions testing on our product and it has failed because of excessive noise in all harmonics of 80MHZ. Some investigation has shown that the ADC output pin area is polluting the board and radiating 80MHZ harmonics through the connected sensor leads.

Reading another user's questions about maximum capacitive load, and the EVAL datasheet, I am asking;

-What can we do to minimise the noise?

-Would placing 22OHM resistors on as per the EVAL board give a noticeable/substantial reduction in noise (Or other value based on calculations for our specific implementation)?

-Is there something else that we should be doing (aside from good/normal PCB layout practises) that we should/could be doing?

Thanks kindly in advance for your helpful reply!



Added tage
[edited by: Disco Inc. at 1:32 PM (GMT -5) on 3 Jan 2021]
  • 0
    •  Analog Employees 
    on Jan 3, 2021 8:51 PM 1 month ago

    Hello,

    Adding series resistor network next to digital outputs (including DCO output) will reduce the rise/fall times of the digital output thus it will also reduce the high frequency content (i.e. spurious content that are harmonics of FCLK).  The actual value of the resistor network will be a trade-off in rise/fall time vs harmonic roll-off.   The series resistor forms a low pass filter with the parasitic capacitance of the PCB trace and FPGA input thus increasing the resistance will reduce  the bandwidth (thus filtering out higher order harmonics).   One try try value of 22 ohms and then increase by 10x (or 220 ohms) to see impact on EMI.   Note one should use O'cope to checking timing of Data vs DCO albeit all these signals will have same series resistor so timing should likely hold if all trace runs are equal.   Lastly.........one could run digital output at 1.8 V (vs 3.3 V), if that is an option.