I would like to ask, the twelve-period delay mentioned here refers to the period interval of the sampling clock, or the first twelve rising edges of the DCO are meaningless data
Thanks for reaching out.
Pipeline delay refers to the number of clock cycles you need to wait to observe the input sample on the digital output. On the very first input sample upon startup, there will be no digital data output on the AD9254 for 12 clock cycles.
The illustration below will help to understand this.
Yes, the first edge of the DCO is the first sampled data.
The timing diagram is just for explaining the concept of pipeline latency.