I have got a question to the timing diagram for the multiplex digital output bus timing for the LTC2291 on page 14.
There are two delay's for the multiplexed timing diagram: tD = CLK to DATA Delay and tMD =mux to data delay.
Now my question is: Is my worst case delay for the output of Channel B when starting from the rising CLK edge: tD + tH + tMD, tH is clock high time?
Does the tMD only belong to the falling edge of the CLK?
I was wondering because I switch from the AD9238 to the LTC2291 and the AD9238 only have a tD delay. Now in my design sometimes chanel a and chanel b were swapped when I only compensate the tD delay. The maximum tD delay time is nearly the same 5.4ns to 6ns.
Thanks for your help,