LTC 2291 Timing Diagram for multiplexed digital output

Hello all,

I have got a question to the timing diagram for the multiplex digital output bus timing for the LTC2291 on page 14.

There are two delay's for the multiplexed timing diagram: tD = CLK to DATA Delay and tMD =mux to data delay.

Now my question is: Is my worst case delay for the output of Channel B when starting from the rising CLK edge:  tD + tH + tMD, tH is clock high time?

Does the tMD only belong to the falling edge of the CLK?

I was wondering because I switch from the AD9238 to the LTC2291 and the AD9238 only have a tD delay. Now in my design sometimes chanel a and chanel b were swapped when I only compensate the tD delay. The maximum tD delay time is nearly the same 5.4ns to 6ns.

Thanks for your help, 


  • +1
    •  Analog Employees 
    on Jan 18, 2021 4:33 PM 2 months ago

    td is the delay from when clock goes high to when the transition happens on the output.  The tMD is the time delay from the falling clock edge to the when the data transitions.  tH is the clock high time but that is controlled by your clock source.  The ADC doesn't alter the period of your clock unless duty cycle stabilizer is on in which the clock period will be the same as what you send it, but the duty cycle will be 50%.