Hi there, I have a board with the LT2325-16 ADC interfacing against a CPLD. I have a problem with the CLK out signal coming from the ADC. When the conversion starts, the clk output signal shows 16 pulses in the oscilloscope but the first pulse does not reach more than 2.5V, the rest 15 clk pulses reach 3V. The CPLD is CMOS and does not register the first pulse as a digital 1.
Is this normal in this component? Or could be related with the board layout? It does not seem to be a problem with board layout as 15 clk pulses are ok.
I have tried to use a pull-up but didn't fix the problem. Any ideas of how to fix this? Thanks in advance.