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Clock problem with ADCLK925 and AD9695/AD9739


I am using AD9695 and AD9739 with an ultrascale FPGA, on custom board.

We have no problem with the design, until we load a high consumption bitsream into the FPGA.

When the a full FPGA is loaded, the input clock (1280MHz) is no longer detected by the ADC AD9695 and the DAC ad9739.

We are using ADCLK925 to feed AD9695/AD9739's input clock, the trace length are15 cm, and passing under the FPGA....

I am thinking  to make a new design using ADCLK914 close to both AD9695 and AD9739, (like on AD9739's evaluation board).

Can it work? can you feed ADC9695 with ADCLK914? can you feed ADCLK914 with LTC6954?

Here is a diagram on the actual and the new design. I would like your opinion on this.

Best Regards

[edited by: RknMgn at 6:53 AM (GMT -4) on 21 Oct 2020]
Parents Reply
  • Because of a bad design and very high consumption of FPGA, DC/DC regulators output is VERY noisy on on FPGAs 0.95V rail. The noise is so high that it pollutes the 1280MHz clock. We have implemented the second solution (ADCLK905 on AD9695 instead of ADCLK914) and waiting for the new hardware to be tested.

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