I have an ad9254 development board with two ad9254 chips integrated on it. When I use it, I find that when I give the same sampling clock (two sampling clocks are separated by a power divider) to two ad9254 chips , The initial phase values they collected are mostly similar, but sometimes there will be a big difference (basically there will be a big difference in 20 or 30 experiments, and then I found that the difference is about a sample Cycle. One of the adcs is slower than the other adc by a sampling period sampling), I don’t know what caused it, if possible, please reply me
Upon inspection of the datasheet, it is unclear why this would be the case if the power divider provides deterministic sampling clocks (i.e. always same phase upon power-up initialization) to the ADC clock input and the input to both ADC's are deterministic at all times. That said...........the latency of the datasheet is specified as 12 cycles typical...................although the latency of these sort of pipeline converter is also considered deterministic in that it should remain fixed.Could the problem be with the data capture device? Lastly...............we would typically recommend that a Dual ADC be used in instances where "simulataneous sampling" between 2 ADC's is desired since this will guarantee best matching characterics between both ADC's which use same clock input as well as matched ADC inputs.