Hi. I use the following product:
HSC-ADC-EVALEZ （fmc interface）
I have fed the same sinusoidal signal in CHA1 and CHB1. Signals are in frequency, phase and amplitude identical (checked on the oscilloscope). In Visual Analog signals are not synchronous phase. What can be the reason for this? Is there a solution?
I expect at the AD converter that all channels are sampled synchronously. Is that correct? Can I reprogram the fpga code?
Yes, you are correct. In the default condition with the internal clock frequency divider set to divide by 1, all channels of the AD9681 will sample simultaneously. The reason they do not appear…
I have requested the code to be emailed to you. You should receive it within a day or two.
Yes, you are correct. In the default condition with the internal clock frequency divider set to divide by 1, all channels of the AD9681 will sample simultaneously. The reason they do not appear synchronized in VisualAnalog is because of the way the capture is done in the FPGA.
Modifying the FPGA program is needed to do time aligned capture. Unfortunately I do not have an FPGA program that does this. I'm sorry about that.
If you are an FPGA developer I can request that the source code be sent to you, if you would like to look at it for possibly modifying yourself.
I'm sorry I don't have a solution for you.
Thanks a lot for your anwer!
I'm a FPGA developer. I can do it by myself, if I have the source code! Please help me to request that the source code of the HSC-ADC-EVALEZ board, which have the FMC port.
My email: email@example.com
I have received the source code! Thanks a lot.
I have modified it, and realized synchronous data acquisition with eight channels.
Excellent!! I hope your project goes well.