How to achieve all channels are sampled synchronously with HSC-ADC-EVALEZ !

Hi. I use the following product:

HSC-ADC-EVALEZ (fmc interface)

AD9681-125EBZ

I have fed the same sinusoidal signal in CHA1 and CHB1. Signals are in frequency, phase and amplitude identical (checked on the oscilloscope). In Visual Analog signals are not synchronous phase. What can be the reason for this? Is there a solution?

I expect at the AD converter that all channels are sampled synchronously. Is that correct? Can I reprogram the fpga code?

Thank you.