My company is going to make a chip targeting the 5G femto-cell. Thus the chip must support the main stream transceiver, like ADRV9026. During the SW investigation, I found the evaluation need to access some driver as
#define BBIC_CORE_REG_PATH "/dev/uio0\0"
#define BBIC_RAM_PATH "/dev/uio1\0"
#define BBIC_SPI_ADV_REG_PATH "/dev/uio2\0"
The HW related to the driver should be some logic in FPGA. And it seems the SW is based on Linux.
The verification FPGA in our lab is also a powerful Xilinx FPGA. And I hope to get your BBIC design details and the related Linux drivers, thus I can use your evaluation SW.
Can you tell my how I can get those info? Thanks