AD9123 MULTICHIP SYNCHRONIZATION in AVERAGED SYSREF MODE

I want to design two AD9123 using multichip synchronization in averaged sysref mode.

One characteristic of  averaged SYSREF synchronization is " No sampling issues due to setup/hold time violations. "

Does this mean that averaged sysref mode may fiter the jitter on the SYSREF signal, but in worst case, without enough setup/hold time, the synchronization between two AD9123 is ± 1 sample clock?