I want to design two AD9123 using multichip synchronization in averaged sysref mode.
One characteristic of averaged SYSREF synchronization is " No sampling issues due to setup/hold time violations. "
Does this mean that averaged sysref mode may fiter the jitter on the SYSREF signal, but in worst case, without enough setup/hold time, the synchronization between two AD9123 is ± 1 sample clock?
The AD9213 digital datapath does not receive any SYSREF pulses until the MCS lock goes high. So, the normal JESD204B subclass1 sequence that rely on SYSREF needs to wait until MCS lock goes high.
Assuming that the same SYSREF signal is presented to both AD9213s, and that the SYSREF signal satisfies the requirements for averaged SYSREF, then the synchronization between two AD9213s will be within +/- 1 sample clock period.
Does this mean that if continuous sysref pulses are sent to AD9213, MCS lock can be achieved at the time when AD9213 recieves "SYSREF_x averaging count" number of pulses?Here are another question.To achieve deterministic latency, the transmitter will send ILAS on LMFC boundary at the time when LMFC is reset by SYSREF.Does AD9213 send ILAS on LMFC boundary at the time when MCS lock is achieved?
Regarding the question about MCS lock after the specified averaging count has been reached, a wait time is needed after the AD9213 is put into SYSREF averaging mode, before checking for MCS lock. This is described in Step 10 of the MCS AVERAGED SYSREF MODE SETUP section of the AD9213 datasheet (RevA). Please see step 10 of this section for how to calculate the MCS lock wait time.
I'm still checking on the relationship of ILAS being sent and MCS lock.
Thank you very much.
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