I am trying to connect the EVAL-AD9656 to a zcu102 board and I cannot find the FMC pinout and IO standards documented anywhere. Do you know where I can find this information so I can create an .xdc for the fpga?
I am trying to connect the EVAL-AD9656 to a zcu102 board and I cannot find the FMC pinout and IO standards documented anywhere. Do you know where I can find this information so I can create an .xdc for the fpga?
Hi Duncan,
Thanks for using the AD9656.
Are you looking for the FMC connector pin assignments for the AD9656 evaluation board, or are you looking at the FMC VITA 57.1 standard pin definitions?
If it is the pin assignments for the AD9656 evaluation board, you can find this in the board schematics. If you go to the AD9656 evaluation board quick start guide ( wiki.analog.com/.../ad9656-125ebz ) and scroll down you'll come to a link underneath the "Design and Integration Files" heading. Clicking on this link will open a zip file that contains a PDF version of the schematic, from which you can get the FMC connector pin assignments specific to the AD9656 evaluation board.
Is this what you are looking for?
Thank you.
Doug
Yes, that's it thanks. I see that the AD9508 and AD9553 is creating the ref clk to the fpga for the 9656 serial data - what's the easiest way to figure out what clock frequency it is running at? I will have the 9656 set to M=4,L=4. Is there an easy way to get what the spi register configuration will need to be for the AD9553 and AD9508?
HI Duncan,
AD9508 is needed in case the AD9656 internal clock frequency divider is used. In that case the clock applied to the ADC will be higher frequency than the sample rate, so then the AD9508 is programmed to divide the clock frequency by the same amount as the AD9656 clock frequency divider, to provide a clock at the sample rate to the FPGA and the AD9553. If the AD9656 internal clock frequency divider is not used (i.e. is set to the default divide-by-1), then the AD9508 can be left in its divide-by-1 state.
The AD9553 provides a multiple of the sample clock frequency to the FPGA as a reference. In the case of capturing on our FPGA board (HSC-ADC-EVALEZ, Virtex6), it multiplies the clock frequency by 4x in our most frequent use case of M = 4, L = 2. For M = 4, L = 4 the AD9553 multiplies the sample frequency 2x. Please keep in mind that the AD9553 multiplication factor is dependent on your FPGA design. The factors above are specific to our capture solution and your requirements will likely be different.
The SPI settings of the AD9553 depend on the multiplication factor and the clock frequency. It contains a PLL so it must be able to lock at the chose frequency. Once you know your ADC sample rate and the multiplication factor needed for your particular FPGA solution, then you can determine the configuration of the AD9553.
A tool that is helpful in determining the SPI register settings for the AD9553 is the AD9553 Evaluation Software. You won't be using this to run the evaluation setup, but it includes a way to determine the configuration of the AD9553 based on user specified frequency and multiplication factor.
FYI here is the link to a related EngineerZone post: https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/20711/hsc-adc-evalez-ad9656-devider-in-matlab
Also FYI, here is the link to an EngineerZone post where I attached a MATLAB example which includes programming of the AD9553 for 125MHz, 4x operation. https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/20750/hsc-adc-evalez-ad9656-matlab-control
Thanks,
Doug
HI Duncan,
AD9508 is needed in case the AD9656 internal clock frequency divider is used. In that case the clock applied to the ADC will be higher frequency than the sample rate, so then the AD9508 is programmed to divide the clock frequency by the same amount as the AD9656 clock frequency divider, to provide a clock at the sample rate to the FPGA and the AD9553. If the AD9656 internal clock frequency divider is not used (i.e. is set to the default divide-by-1), then the AD9508 can be left in its divide-by-1 state.
The AD9553 provides a multiple of the sample clock frequency to the FPGA as a reference. In the case of capturing on our FPGA board (HSC-ADC-EVALEZ, Virtex6), it multiplies the clock frequency by 4x in our most frequent use case of M = 4, L = 2. For M = 4, L = 4 the AD9553 multiplies the sample frequency 2x. Please keep in mind that the AD9553 multiplication factor is dependent on your FPGA design. The factors above are specific to our capture solution and your requirements will likely be different.
The SPI settings of the AD9553 depend on the multiplication factor and the clock frequency. It contains a PLL so it must be able to lock at the chose frequency. Once you know your ADC sample rate and the multiplication factor needed for your particular FPGA solution, then you can determine the configuration of the AD9553.
A tool that is helpful in determining the SPI register settings for the AD9553 is the AD9553 Evaluation Software. You won't be using this to run the evaluation setup, but it includes a way to determine the configuration of the AD9553 based on user specified frequency and multiplication factor.
FYI here is the link to a related EngineerZone post: https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/20711/hsc-adc-evalez-ad9656-devider-in-matlab
Also FYI, here is the link to an EngineerZone post where I attached a MATLAB example which includes programming of the AD9553 for 125MHz, 4x operation. https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/20750/hsc-adc-evalez-ad9656-matlab-control
Thanks,
Doug