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AD9446 LVDS output questions


Our customer has question on the AD9446, please see below.

We are using the Analog AD9446BSVZ-100 ADC with LVDS outputs for this project..  Both the data bus outputs

And the clock output have the same timing range (2.1ns – 4.8ns). 


  1. Is it possible for some of the 16 output data bits to be valid before the output clock (DCO+/-) edge and other data bits to be valid after the output clock edge?  Is there some guarantee that the data will transition only after the output clock?
  2. Is the data output clock (DCO+/-) a free running output clock, or is it valid only when there is valid data on the output data bus.  Or is there some other timing involved?


Thank you.

Best Regards,