AD9681 xilinx ultrascale data capture HDL code.

Hi Silmang,

Thank you for using the AD9681. I'll request sample Verilog FPGA capture code to be emailed to you.

It will take a few days.

Thank you.

Doug

Thanks Dougl. 

I received the file you sent me well.

The code you sent me is for virtex6, do you have any code for UltraScale?

It doesn't matter if it's code for capturing data from other adc, not just for ad9681, 

Hi Silmang,

I'll ask for an UltraScale example.

Thanks,

Doug

Hi Silmang,

The only sample FPGA code we have for UltraScale is for capturing JESD204B/C ADC outputs; the JESD IP from Xilinx will have been removed. The AD9681 has serial LVDS outputs which is quite different from JESD.

The ADC interface portion of the Virtex6 code that we sent to you will be essentially the same the same as ADC interface code written for UltraScale.

Are you looking for an example of how to capture serial LVDS outputs?

Thank you.

Doug

Hi Silmang,

The only sample FPGA code we have for UltraScale is for capturing JESD204B/C ADC outputs; the JESD IP from Xilinx will have been removed. The AD9681 has serial LVDS outputs which is quite different from JESD.

The ADC interface portion of the Virtex6 code that we sent to you will be essentially the same the same as ADC interface code written for UltraScale.

Are you looking for an example of how to capture serial LVDS outputs?

Thank you.

Doug