Hi. I'm using AD9681.
I want to capture data with xilinx ultrascale FPGA .
Is there any HDL code for this?
The only sample FPGA code we have for UltraScale is for capturing JESD204B/C ADC outputs; the JESD IP from Xilinx will have been removed. The AD9681 has serial LVDS outputs which is quite different from JESD.
The ADC interface portion of the Virtex6 code that we sent to you will be essentially the same the same as ADC interface code written for UltraScale.
Are you looking for an example of how to capture serial LVDS outputs?