AD9251 inleaved output mode


Please help me.

I have some question about interleaved output mode.

1. To enable output mux, all I need to do is set bit 5 of register "Output mode" (0x14)?

2. Once the output mux of AD9251 is enabled, the two digital output (A/B) will output the same waveform?

Thank you for the support!

Best Wishes,


  • Hi William,

    The Interleaved output mode is enabled globally onto both output channels via 0x14, bit 5. The

    undesired channel output can then be disabled by selecting the desired Channel (A or B) Index at 0x05,

    bits 1-0, then writing a 1 to local (channel specific) OEB register 0x14, bit 4.

    The default operation of interleaved (DDR) mode outputs chA port data as ADC_A/B as shown in d/s

    fig 3 and outputs chB port data as ADC_B/A (not shown in d/s), although this can be reconfigured by

    the customer to either A/B or B/A sequence using the “output Invert” bit 0x14, bit 2.

    So in interleave mode (d/s fig 3) the respective A or B data is output for only ½ of the CLK period,

    latched by both the rising and falling edges as opposed to the non-interleaved mode shown in fig 2.



  • Rob,

    I am having trouble reproducing the multiplexing functionality.  I run the following commands which seem to have some effect in disabling port B output however the data on port A appears single rate rather than being clocked out on both rising and falling edges.

    1. 0x001420 - Write 0x20 to address 0x14 to select interleaved mode.

    2. 0x00FF01 - Commit shadow register values by writing 0x01 to address 0xFF

    3. 0x000502 - Select converter/channel B by writing 0x02 to address 0x05

    4. 0x00FF01 - Commit shadow register values by writing 0x01 to address 0xFF

    5. 0x001410 - Disable channel B output port by writing 0x10 to address 0x14

    6. 0x00FF01 - Commit shadow register values by writing 0x01 to address 0xFF

    I have tried several configurations steps including committing the shadow register values periodically but encountered similar results.  Is there another trick to getting DDR output on port A?

  • Hi Doug,

    Your probably right, I had tried a bunch of different settings and one of them was to disable multiplexing on one channel but not the other in thinking it may have a directional (A->B vs B->A) effect.  I noticed the DCO output would only output a low duty cycle pulse instead of square wave which shifted the focus to the clock input.  Turns out one of the differential input lines was partially shorted under the package causing the apparent input seen by the chip to be distorted but still partially function somewhat erratically.  The part was reflowed and seems to be working well now.

    Ended up implementing a reset sequence followed by the mux setting which seems to work:

    1. x"000024" - Chip reset by setting register 0x00 to 0x24

    2. x"00FF01" - Update shadow registers by writing 0x01 to 0xFF

    3. x"000503" - Select both channels A & B by setting register 0x05 to 0x03

    4. x"00FF01" - Update shadow registers by writing 0x01 to 0xFF

    5. x"001420" - Enable multiplexing by writing 0x20 to 0x14

    6. x"00FF01" - Update shadow registers by writing 0x01 to 0xFF

    I am not sure the updates to register 0xFF are necessary but simply left them in there because it seems to work and isn't significant in this app.


  • 0
    •  Analog Employees 
    on Aug 28, 2012 9:01 PM over 8 years ago

    Hi deepblue,

    What I think is happening is that when you do the second write to Register 0x14, you are writing over the previous contents and de-asserting multiplex mode by writing 0x10, thus writing a "0" to bit 5.

    Also, I don't think the shadow register transfer register is needed here.

    Please try the following sequence:

    1. Register 0x05 = 0x02

    2. Register 0x14 = 0x03

    Please let me know if this works. In parallel, I'll be trying to get this going on my bench to confirm.



  • 0
    •  Analog Employees 
    on Aug 28, 2012 11:06 PM over 8 years ago

    Hi Jason,

    Nice work! I'm very glad you got it working.

    The only thing I would mention is that, when doing the soft reset with Register 0x00, I use the value 0x3C instead of 0x24. Both of these values set the reset bits, but the default mode is to have bits 3 and 4 a "1", which 0x3C does.

    Obviously 0x24 is working for you; I'm just sharing what I typically do.

    I wish you the best for your project. Please let me know if you need any more information. I'll do my best to get it.

    Take care,