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AD9211 in ddr mode

I use AD9211-200 adc in ddr mode with Cyclone III FPGA, and have problem with digital data interface. The image shows data that i get from adc for sample rate 200 MHz and input sine wave 200.05 MHz.

Bit 0 from adc allways zero. Bits 4 and 5 are not consistent.

In what may be the problem?

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  • In the original datasheet of AD9211 there is still the same mistake for DDR pinout that was reported here more than 5 years ago. So now I have to make a new pcb...


    There is another mistake in the same datasheet on p. 23 (CONFIGURATION WITHOUT THE SPI). In this section it is written: "In this mode, the SPI CSB chip select should be connected to ground, which disables the serial port interface."

    But it should be: connected to AVDD!

    Please fix your datasheets!!!

Reply
  • In the original datasheet of AD9211 there is still the same mistake for DDR pinout that was reported here more than 5 years ago. So now I have to make a new pcb...


    There is another mistake in the same datasheet on p. 23 (CONFIGURATION WITHOUT THE SPI). In this section it is written: "In this mode, the SPI CSB chip select should be connected to ground, which disables the serial port interface."

    But it should be: connected to AVDD!

    Please fix your datasheets!!!

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