AD9262 SPI programming

Hi,

I am using AD9262 together with Blackfin ADSP-BF548. The SPI port of the processor is used to connect to the serial configuration port of the ADC. I took the exact circuit used in the AD9262 evaluation board to connect ADC's SDIO/SCLK/CBS to the MISO/MOSI/SCLK/slave select of processor's SPI port. When I tried to read the configuration registers of the ADC, it looks like the ADC is not driving the SDIO at all. I used a scope to probe all the SPI signals. They are all what I expected and consistent with the app note AN-877 diagram. Only problem is the read data phase, where it looks like the ADC does not drive SDIO at all, and the SDIO signal stays the same as whatever is driven by MOSI. Is there any possible reason for this?

I speculated something:

1. The ADC is not working at all. But I examined all the power and clock supplies to AD9262 and everything is fine. And there is DCO output. How can I verify if the ADC is working well and supposed to respond to the SPI register read command?

2. The SPI circuit of AD9262 evaluation board might not be good. During the read data phase, both ADC and processor are driving the MISO, and the processor is driving it through a resistor R3. The value of R3, 1.07K, might be too small and so processor drive strength overrids SDIO of ADC.

Any idea is appreciated!

Here is some more details on my system: the ADC is on my own board and the DSP processor is on ADSP-BF548 EZKIT. The two boards are connected through the extension connector J1, J2 and J3 of the ADSP-BF548 EZKIT.

thank you very much.

Coolparam

  • 0
    •  Analog Employees 
    on Feb 22, 2012 11:46 PM

    Hello,

    Answers to your questions are as follows:

    1) Try doing a software RESET as 1st set of commands followed by a SPI command that powers-down the device.  Assuming you can measure the reducing in power consumption (i.e. monitoring external supply current), you can confirm if a WRITE operation is working properly.

    The sequence would be as follows:

    0x00  0x18

    0x00  0x3C

    0x00 0x18

    0x08 0x01

    2) During the latter 1/2 of the READ operation (after instruction portion)........data should be driven onto the SDIO bus on 1st falling edge after A0 bit is read).  Try reading Reg 0x01 (Chip ID)........which should be 0x22) and see if the SDIO pin of the AD9262 attempts to go high for the "00100010" output sequence.

    3) Seems like you are fly-wiring the SPI connection between boards.  Ideally, you want a ribbon cable that also includes a some wires that are dedicated ground connections (i.e. connects the digital ground planes of both boards).  Also, it is best to opearate with a "slow" SPI clock frequency ( below 100 KHz) if the "quality" of the SPI signals is not good (i.e. spikes, overshooting, ext).  Note, make sure the o'scope trace bandwidth is set to full when examining these lines.............to ensure that  "voltage spikes" that could be causing a problem remain visible with the o'scope.

    Regards.

  • Hi PMH,

    Your advice is very very helpful.

    1. I did not break the power supply trace on the board to measure the current, instead I scoped the output of DCO of the ADC. Is this approach Ok?  The power-down sequence did not disable the DCO output. Does that mean that the writes of SPI are not accepted by ADC?

    2. The readouts of any registers are always the value the process drives to SPI MOSI.

    3. The SPI connections are traces on boards.


    By the way, if the ADC did not accept any SPI configuration command, I assume it should be working on directly CLK mode and use the CLKIN as sampling rate. My CLKIN is 32MHz, I assume the DCO output should be 32MHz/64=500KHz. Am I right? Is the DCO output supposed to be constant square waveform? I scoped the DCO and it looks like a bursty square waveform of frequency 8MHz. Is that what you expect? Does this observation ring any bell to you?

    In addition, I have a GPIO to control the RESET of the ADC. When I pulled it high to reset the ADC, I can see the DCO output is disable - all ground. Is that expected?

    Sorry for so many questions. I am desperate. :( Thank you very much.

    coolparam

  • 0
    •  Analog Employees 
    on Feb 23, 2012 11:16 PM

    Hello,

    On our evaluation board, I was able to observe a 8 MHz DCO output (stable, not bursty) with CLKIN of 32 MHz after power-up thus this appears to be the default relationsip between CLKIN and DCO until the KOUT factor (Reg0x101) is programmed.

    Note, in the SPI sequence I described above...................a single WRITE to Reg 0x00 of 0x3C is sufficient to RESET the device since the "RESET" bit is not sticky (i.e. self toggling) such its value returns to 0x18 after this signle WRITE operation.

    Anyways.......one should see a stable 8 MHz DCO clock (assuming stable 32 Mhz CLKIN) after power-up and one can make the DCO clock disappear by by writing 0x01 to Reg 0x08 (Power-down).  If DCO does not disappear than this would indicate that a SPI WRITE is not occuring.

    If this is the case, try the following:

    1) Check voltage levels of SPI lines to ensure they meet datasheet specification.

    2) Reduce SPI clock frequency and ensure that no "glitching/spikes" are occuring on the line that could corrupt data transfer.

    Lastly, setting RESET high should cause the DCO output to disappear since this input is not self-toggling (unlike the SPI register bit).

  • Hi PMH,

    Thank you very much for your answer. But my system is still  not working. Some more questions:

    1. Right after power up of the ADC, without any configuration, is the ADC running the default A/D conversion with sampling rate of 8MHz (if clock in is 32MHz)?

    2. In what possible conditions, could the ADC driver a bursty DCO? - related to the following question.

    3. When my ADC board is powered up alone, it drives DCO normally. But when I plug my ADC board to the processor evaluation board, the DCO becomes bursty, even when the processor evaluation board is powered off ( so there could not be signal conflict between ADC and processor). Do you have any idea? I understand this is a question very hard to answer. Sorry. Any thought would great appreciated?

    thank you very much

    coolparam

  • 0
    •  Analog Employees 
    on Feb 29, 2012 4:38 AM

    Hello,

    I would expect that the device provides a DCO clock that is 1/4 of the ADC clock upon power-up.  Seems like you are seeing this also when your board is not connected to the DSP board.

    As mentioned above, RESET will cause the DCO signal to disappear upon going high.  RESET should not be a floating..................you should check with o'scope that this input is at DGND with minimal noise that could cause it to trigger (i.e. threshold around 0.9 V when DRVDD=1.8 V).

    Have you confirmed that you can perform a SPI WRITE/READ operation?