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AD9627, output data port layout routing


I am trying to create the layout for AD9627. I am confused with routing AD9627 output data port.

Since this is high speed ADC the data port should also be high speed and should be able to support high speed communication. My question here do we need to do length matching between dataport of ADC?

This question is in relation with DDR routing where we need to do the length matching i.e. the maximum difference between length of data port cannot be more than 50 mil.

Should I apply such rule here

  • Yes, you do need to be aware of matching lengths of the digital outputs and the data clock.  Matching is important to ensure that the data is aligned and can be received properly.  The actual matching required depends on a number of factors including PCB velocity factor, PCB trace length and the setup and hold times for the ADC and the receiver device. 


    The AD9627 can be configured for LVDS or CMOS output mode.  Depending upon the configuration you choose observe the setup and hold time for the ADC digital output and that of the receiver to align the latching edge of the clock relative to the data.  The better you can match the lines, the better off you will be to meet timing requirements.  If you can maintain the 50 mil matching on the digital lines, it will minimize skew between the signals and will minimally impact the timing requirements of the signals.