Pin-SYNC with DDC?

What register settings should work for getting a AD6636 DDC to correctly sync and activate a DDC channel - using a low-to-high transition on a SYNC0 pin?

At the moment I can get SOFT sync working no problems, and have poured over the data sheet, looking for clues as to why the "pin sync" settings ( as per data sheet) arent working. Its a simple single channel, single input system.

Thanks for any info.

Dave

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    •  Analog Employees 
    on May 7, 2012 7:44 PM

    Hi Dave,

    When the AD6636 was initially released it may have had an edge over an FPGA in terms of power/function, but FPGAs are continually evolving to smaller process geometries which leads to lower power.  So I expect today's FPGAs would likely come in at lower power than the AD6636 for the same function.  I have not done a head to head evaluation to confirm this either.

    Michael

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  • 0
    •  Analog Employees 
    on May 7, 2012 7:44 PM

    Hi Dave,

    When the AD6636 was initially released it may have had an edge over an FPGA in terms of power/function, but FPGAs are continually evolving to smaller process geometries which leads to lower power.  So I expect today's FPGAs would likely come in at lower power than the AD6636 for the same function.  I have not done a head to head evaluation to confirm this either.

    Michael

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