AD9446 and AD8139

Hello,

I,m a young application engineer for LXT-Credence company.

I have design for a customer who wants to test infra red sensor, a loadboard.

As the sensor delivers an output analog signal, and contains 288x384 pixels, I decided to use an ADC to be able to capture all the results thanks to the Digital board of my tester (cause of memory depth needed-arround 11Mo, and the data analyze to do).

This sensor works at a frequency up to 10 MHz. We choose to test the device a 6MHz using an ADC driven by a Differential Amp (converting single ended signal to differential signal). The analog output of the sensor is from 1.0V up to 4.2V.

With this frequency and the analog range, I decided to choose the AD9446 as data converter.

To drive this ADC, I choose the AD8139 and I create the following :

The analog supplys of the AD8139 are +7V and -3.8V.

Here is the AD9446 used :

The clock frequency of the ADC is 60MHz, but I can only capture one data every 6MHz because of the output sensor settling time.

I currently have a standard deviation of 5.6mV for each pixel of the sensor with this application board (each pixel measured 100times). The real value of the standard deviation of pixel sensor is about 200uV.

To correlate with the real value of the sensor, I have to place a 22nF capacitor between the two ADC input, creating a 300KHz low pass filter.

My question is the following :

Do you think that the 60MHz ADC clock can generate as much noise on the ADCinputs?

What could be a good method to create a 6MHz low pass filter with a high rejection of the 60MHz (RC between inputs, RC between inputs and supply voltage, RLC only) ?

Do not hesitate if you do not understand some points.

Thanks on advance.

  • 0
    •  Analog Employees 
    on Jun 12, 2012 6:20 AM

    Hi Frederic,

    Thank you for the beautiful explanation of your problem. If I understand correctly, you have two concerns/questions:

    1. Does the 60MHz ADC clock generate any noise at the ADC inputs?

    Typically no. A lot of this would depend on the board layout. If there is proper isolation from the clock signals to the ADC inputs the clock should not create any noise at the ADC inputs. Are you seeing any noise at the ADC inputs?

    2. What is a good method to create a 6MHz low pass filter?

    There are many ways of doing this. I can help you with this if you want. In order to define the filter, you would need the following:

          - Bandwidth F(-3dB) (in your case it is 6MHz right?)

          - Pass band flatness or ripple

         - stop band rejection A(-3dB) (you specified the frequency of 60MHz, but not the rejection)

          - order of the filter. this is dependent on the stop band rejection. The higher the number, the more components are needed.

    Hope this helps. Let me know if you need help with the filter.

    Regards

    Umesh

  • Hello Umesh,

    "1. Does the 60MHz ADC clock generate any noise at the ADC inputs?

    Typically no. A lot of this would depend on the board layout. If there is proper isolation from the clock signals to the ADC inputs the clock should not create any noise at the ADC inputs. Are you seeing any noise at the ADC inputs? " In fact the layout is not very good and I have the CLK signal in parallele with the Diff amp during arround 5-6mm and very close.

    "2. What is a good method to create a 6MHz low pass filter?

    There are many ways of doing this. I can help you with this if you want. In order to define the filter, you would need the following:

          - Bandwidth F(-3dB) (in your case it is 6MHz right?)

          - Pass band flatness or ripple

         - stop band rejection A(-3dB) (you specified the frequency of 60MHz, but not the rejection)

          - order of the filter. this is dependent on the stop band rejection. The higher the number, the more components are needed."

    CurrentlyI have added on my schem two low pass filter : the first one is done on the Diff Amplifier using a 47pF capacitor and a 120 Ohms resistor (F[-3dB]=28MHz) and the second one is between the Diff amp outputs and the Diff ADC inputs using a 25 Ohms on each line and a 470pF capacitor between the two lines (F[-3dB]=15MHz). What do you think about those two ? As I have two measure DC voltage each 6MHz, do you think that the two filter have a right cutting frequency ?

    Do you think I also need a stop band rejection to remove the 60MHz ? I don't want to put to many components, so I will limite to first order.

    Thank you for your response and let me know your feeling about my schem.

    Frederic

  • 0
    •  Analog Employees 
    on Jun 13, 2012 5:44 AM

    Hello Frederic,

    - You may want to rethink your layout strategy and somehow isolate the clock lines from the analog inputs. The AD9446 is a high dynamic range part and at 16-bit resolution and full-scale of 3.2Vpp, the LSB is about 50uV. So it is critical that the analog input traces are fairly isolated from the clock signals. I will send you the gerber files for the layout we did on our evaluation board for reference. Please note that the evaluation board layout for the AD9446 was done quite a while ago, and it may not be manufacture-able by today's standards. But you can still use it to get a general idea of the placement of the analog and clock traces.

    - On paper I dont see any problems with your filter approach. I am not familiar with the type of signal coming from your transducer, but if it has sharp edges (rise/fall times) which have information you need, you will have to examine the filter setup (cut-off frequencies) to accommodate these edges. Alternately, you can simulate the front end arrangement (diff amp plus filter plus ADC) and see if you get enough rejection at 60MHz. ADI has partnered with National Instruments and released a version of Multisim Component Evaluation ADI edition. This free tool can be downloaded here: http://www.analog.com/en/amplifier-linear-tools/multisim/topic.html

    Here is the filter I mocked up in multisim per your schematic:

    Here is the frequency response of this filter:

    If you want more stop band rejection, you may want to consider a higher order filter (L-C for example).

    Other questions I have:

    - How critical is it that you have a buffered ADC? We have a whole portfolio of unbuffered low power ADCs that can fit your application. The AD9266 (http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9266/products/product.html) is a good example. This part offers the same (or better) performance at lower power. This is just a suggestion.

    Please feel free to contact me if you have any further questions.

    Regards

    Umesh

  • Thank you very much for your support.

    Can you indicate me what kind of SMD inductance can be used for an LC filter ?

  • 0
    •  Analog Employees 
    on Jun 13, 2012 3:25 PM

    We have had good performance with the 0603CS series inductors from coilcraft.

    Regards

    Umesh