AD9629 readout issues.

Hi there:

I'm using the AD9629-40 in a non SPI configuration, and I'm seeing a behavior I can't explain on the ADC bit stream with bursts of bad ADC values (about 40us every 500us) which can not be attributed to readout issues (bursts actually probed on the bus) nor from analog from end issues (inputs connected both to clean VCM).

  I thought the ADC was operated in its Test mode (0x0D) so I set this register to 0x00 to make sure this mode was off, but this was not sucessful. I also replaced the ADC, but this was also not successful. Clocking it at slower speed did not help.

  I'm a bit clueless here; has anyone experienced that type of behavior?

Thanks.

Anthony.

  • Hi Doug:

    Thanks for your help. This is below a snapshot of the AD9629-40 sub-section. The logic section is instrumented using a cyclone IV FPGA, and the nyquist filtered analog signal is centered around the VCM voltage. Without SPI control, ADCPWDN is tied to GND and ADCCSB is tied to +1.8V.

    Below is the bit "ADC8" probed after R25 on the scope when VIN- and VIN+ are tied to VCM.

    Are you aware of any power sequencing requirements in a non-SPI configuration?

    Best regards,

    Anthony.

  • 0
    •  Analog Employees 
    on Jun 13, 2012 9:20 PM

    Hi Anthony,

    You have an interesting problem indeed. I have not experienced this particular behavior, but I am confident we can get to the bottom of it. Are you at liberty to share your schematic of the ADC and surrounding components? If not, we can still proceed by obtaining additional information about your system.

    Thanks,

    Doug

  • Hi Doug:

      If possible, I'd like to make it work in a non-SPI configuration first, which also sounds easier to troubleshoot.

    1- Are the supplies being brought up separately/independently?

    Yes, the Analog 1.8V and Digital 1.8V are produced independently; they share a common ground.

    A few more questions:

    2- How is the SCLK/DFS pin connected/driven?

    SCLK/DFS is driven low by the FPGA in the non SPI configuration, and controlled according to the AN-877 in the SPI configuration.

    3- How is the MODE/OR pin connected/driven?

    MODE/OR is used as Out of Range bit input to the FPGA in the non SPI configuration.

    - Is the VCM pin capacitively bypassed to ground?

    VCM is bypassed to ground through 0.1uF, 1uF and 10uF ceramic capacitors

    - Is the VCM pin supplying the input common mode voltage? If not, what is the input common mode voltage?

    The VCM pin does indeed supply the input common mode voltage.

    - You mentioned writing to register 0x0D. In your system are you able to read/write registers?

    I've implemented a write SPI mode only. Since I'm monitoring the current of the board, I'll try to use tomorrow the power down mode to see if I'm writing effectively.

    Thanks,

    Anthony.

  • 0
    •  Analog Employees 
    on Jun 14, 2012 1:18 AM

    Hi Anthony,

    Thank you for the information. There are no power sequencing requirements that I am aware of. Are the supplies being brought up separately/independently?

    A few more questions:

    - How is the SCLK/DFS pin connected/driven?

    - How is the MODE/OR pin connected/driven?

    - Is the VCM pin capacitively bypassed to ground?

    - Is the VCM pin supplying the input common mode voltage? If not, what is the input common mode voltage?

    - You mentioned writing to register 0x0D. In your system are you able to read/write registers?

    Thank you.

    Doug

  • 0
    •  Analog Employees 
    on Jun 14, 2012 5:37 AM

    Hi Anthony,

    Thank you for the information. There is nothing obvious so far.

    Verifying your register write capability will be a good thing to do. Please keep in mind address 0x08 to address 0x18 are "shadowed". This means that writes to these addresses are not invoked until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

    More questions:

    Regarding the "bursts" observed on the output, is this actual digital switching with the appearance of data? If so, is the pattern and number of pulses the same every time? Is the interval between "bursts" always the same?

    Does this phenomenon also occur when an AC signal is applied? Perhaps with both inputs at VCM (0V differential) we are sitting right on the edge of a major code transition.

    Are you able to observe that your clock is continuous and clean?

    Please let me know how the register writes go.

    Thanks,

    Doug