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AD6624: Question about SCLK0 operation after RESET

Hi, we have an application where the AD6624A is configured (hardwired) for SCLk0 as master. We are seeing some unexplained behavior of the SCLK0 signal at lower temperatures. If the SCLK0 is setup (through the external pin) as a master, and the divisor is also hardwired; how soon after the RESET line (hard reset) is de-asserted should the SCLk0 signal be present? Is there additional activity/command(s) needed to be sent to the chip for this signal to be present? We've monitored the input clock to the AD6624A and we see it's always present; but for some reason the SCLk0 signal is only present sometimes at low temperatures (around -40C we see this behavior, above -30C we see SCLK0 signal always be present).