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AD6624: Question about SCLK0 operation after RESET

Hi, we have an application where the AD6624A is configured (hardwired) for SCLk0 as master. We are seeing some unexplained behavior of the SCLK0 signal at lower temperatures. If the SCLK0 is setup (through the external pin) as a master, and the divisor is also hardwired; how soon after the RESET line (hard reset) is de-asserted should the SCLk0 signal be present? Is there additional activity/command(s) needed to be sent to the chip for this signal to be present? We've monitored the input clock to the AD6624A and we see it's always present; but for some reason the SCLk0 signal is only present sometimes at low temperatures (around -40C we see this behavior, above -30C we see SCLK0 signal always be present).

  • Hi,

    We’re not aware of any issues with the AD6624 starting up at cold temperatures.  We are working with one of your colleagues off-line on the process for returning the suspect parts for analysis. 



  • Many thanks to the folks at ADI. The issue we were tracking was as described above, but was only seen in two parts. Our design attempted to ensure a power sequence where VDDIO was assured to always come in after VDD was above the desired level. In our implementation VDD had a slow ramp-up which made the VDD-to-VDDIO relationship not deterministic. There is nothing on the datasheet which states such a sequence is needed. And there is little to none evidence on our design. For the two CCAs which had the two suspect parts, we ended up adding a fixed delay between the VDD and VDDIO, to ensure that VDDIO always came in after VDD. Again, this is more of an empirical "fix" with very little to back it up (other than the two CCAs are working ok again).