AD9613

Question

Hi, 
 I want to use AD9613 for my dual channel application. I have seen two flavors in ad9613 interleaved parallel lvds and channel multiplexed even/odd lvds. I want to understand 
 1. why now there are lvds output for high speed adc/dac?. I understand that lvds are for noise reduction and can easily applied to fpga etc. 
 2. I used ad9248 with two channels for a similar application. is ad9613 be used as ad9248 with dual channel output? 
 3. so is it like if i apply I and Q channel analog signal to ad9613 i get the output on these lvds? 
 4. should i definitely have the lvds layout on the data lines which are running to fpga? 
 5. what is difference between channel multiplexed and interleaved? 
 Thanks for replying

J.Harris · Accepted Answer

Hi, 
 The AD9613 has two data output modes, parallel interleaved and channel multiplexed. The parallel interleaved mode presents each data bit D0, D1, ... Dn on an output pair where the Ch A bit is output on the rising edge of DCO and the Ch B bit is output on the falling edge of DCO. So on a given output pair you would have DnA, DnB on the rising/falling edge of DCO respectively. In channel multiplexed mode, the Ch A and Ch B data is presented on different output pairs. For a given output pair, even and odd bits are presented where the even bit, DevenA, would be on the rising edge of DCO and the odd bit, DoddA, would be on the falling edge of DCO. 
 1. LVDS outputs are used in higher speed converters because the drivers are more power efficient than CMOS and as you mention offer common mode noise rejection and are easily interfaced to FPGAs. 
 2. The AD9613 can be used with dual channel output, is there something more specific you are asking for here? 
 3. The AD9613 can be used in an I/Q system. 
 4. I am not quite sure what you might be asking here, but you do want to make sure to layout the differential lines to meet the required differential impedance of 100ohms. I would also recommend trying to keep the path lengths similar (to within say 50-100mils) which will ease alignment of the data in the FPGA. 
 5. I think this is answered in the first paragraph above. If you have further questions, please feel free to ask. 
 Regards, 
 Jon

Electronic Design Services - PartnerZone

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AD9613