Post Go back to editing

AD9978A - code needed for start-up and LVDS testing

Hi All,

I have some questions regarding what is required to test the LVDS. It's not clear from the datasheet which registers need to be written to before the test specific registers are written to.  Before I discuss that I will give some details on the digital setup I have.

I'm using a TI micro-controller to do the writing via one of its SPIs at 1Mhz.  However there is a limitation to the SPI write, the TI micro-controller can not write 24bits straight as its buffers are 16 bits long. To get around this I've amalgamated the SPI data into 2x12bit data writes (LSB of address first) with external code controlling the chip select (SL) pin either side of each 24bit write, in this set up as the write is all within a single "transfergroup" where the clock should continue until the last bit is written.  All other options will cause a situation where the clock will idle while the SL pin is still held low, depending on how the "transfergroups" are set this would occur between the Address, Data and ID writes or if a continuous write was attempted the idle would occur between the initial address and the proceeding data and ID writes.

I believe the setup I've selected will produce the the most consistent results.

As for the coding of the AD9978, I've looked at the example code within the datasheet and tried to apply it to the testing code which is discussed, the code below is in the [Address,Data,ID] format.

50 001 F   //SW_RESET
41 102 F   //black clamp enabled, power on REFBUF, start up reg
4E 040 F   //start-up write
4E 040 F   //start-up write
E9 060 F   //start-up write
A3 001 F   //Double Port, Low on DOUT0 & DOUT2 with no delay
A4 060 F   //LVDS MSB first, clipping disabled, TCLK NonInv & set to Mode 3 
B6 0AA F   //Set TCLK_PATT_LO to AA
B7 055 F   //Set TCLK_PATT_HI to 55
B8 001 F   //Enable TCLK pattern mode
B5 402 F   //Enable LVDS pattern for channel A & B
E3 A00 F   //Four LSBs of fixed pattern for AFE outputs
E4 A00 F   //Four LSBs of fixed pattern for AFE outputs
42 004 F   //Enable CLK-OUT
40 000 F   //normal opertation
53 001 F   //power up TG core
A2 000 F   //power on LVDS (TCLK & DOUT[3:0]) drivers

Is this correct?  Any comments would be gratefully received.

Parents Reply Children
No Data