AD9272 source code

Hi Gordon,

The FPGA code for the AD9272 is the High_Speed_Octal_synchronous_capture.zip and Low_Speed_Octal_synchronous_capture.zip.  The low speed version is used for sample rates below 30Msps.

I am sorry but we do not support the software for the CY7C68013A or the PC.

Regards

Gina

Hi Gina,

Can you supply the CY7C68013A source code for reference, I understand that it is unsupported.

Is it the same as: http://ez.analog.com/message/15091#15091

Hi,

No, the evaluation platforms for those products are based on different software / firmware, and would not be applicable for the AD9272 evaluation platform. 

Regards,

David

Hi,

Can I confirm that the High_Speed_Octal_synchronous_capture.zip code is for a 14 bit ADC and that I need to modify it slightly to work with the 12 bit AD9272?

Also, what voltages can I safely put into the LNA inputs on the AD9272 evaluation board (i.e. the sma connectors)?

Cheers, Gordon

Hi Gordon,

Lookig through the Verilog code, in Top.v 2 bits from the input SPI_Register set a variable called bw_bits.  In fifo8k.v, bw_bits is decode for 8, 10, 12 or 14 bits of data.  The output bus, dout is always 16 bits but bw_bits selects how many bits are written though to dout.  When I use this FPGA code with 14-bit or 12-bit devices, I only change the information in SPI_Register to select the appropriate bit width.  The slight modification I would make if you are only going to use it with the AD9272 is to set bw_bits to '10'. 

The LNA input of the AD9272 has an absolute maximum of approximately 3Vpp.  However, the evaluation board has diodes (MMBD4148) that limit the LNA input to ~1.4Vpp.  The diodes have a very high breakdown voltage of typical 75V.  I would limit the voltage onto the LNA input connector to 3Vpp just in case the diodes get removed or have a poor solder connection. 

Please let me know if you have other questions.

Gina