When running the AD9251 with interleaved output data multiplexed onto a single bus, the respective A channel or B channel data is output for only ½ the clock period.
In this case, should we expect to see a rising edge on DCOA to indicate valid Channel A data and then a similar rising edge on DCOB approximately ½ a clock period later to indicate valid Channel B data? This is not clear to us from the timing diagram shown in Figure 3 of the datasheet.
And, should the rising edge occur roughly during the midpoint of the valid data? According to the figure, the rising edge occurs closer towards the tail end of the valid data. Should the frequency of DCOA/B be the same as the frequency of the CLK+?