AD9639 serial stream

Good morning (well, here anyway),

I'm having some issues with a JESD204 stream using an AD9639. The stream from the ADC eval board is working correctly. I've got a HSC-ADC-EVALCZ (Altera variant) capture board, and laid out my own prototype digital rx board. I'm using Visual Analog to capture streams and view data. The first thing I see is a bit toggle of the LSB when selecting test modes (MS short, +FS short, -FS short, checkerboard). All other bits in the 12-bit data are correct. The second issue I've noticed is erratic data when applying a none waveform at the input (a triangle was @ approximately 15kHz 700mVp-p, in this case). Images below.

I've been trying to debug possible clocking and physical hardware issues, but am getting more confident that there is no issue there. I've even jumped differential clock pairs from the ADC eval board across to my prototype to confirm that the clock distribution network (using an AD9510) isn't the issue. Behaviour is the same.

There are obviously plenty possible issues, but one other thing I'd like to confirm is that there are no potential issues with date of manufacture of the IC since it seems the JESD204 standard was evolving recently. Not sure if this is the date code, but the IC I've got on my prototype has #0938 (38th week of 2009) as code, with the eval board having #1103 (3rd week of 2011).

Thought I'd get the ball rolling here since I get no response from cic@analog.com.

Thanks in advance,

Thomas

Parents
  • Hi Jonathan,

     

    As I understand it, the JESD204 standard only covers streams to 3.125GBps. How can the AD9639 then be compliant with JESD204 when it operates at a maximum of 4.2GBps?

     

    Can you confirm whether any other default registers not mentioned in the datasheet need to be set for correct operation? Why are there so few JESD registers for the AD9639 (1) when the AD9644 (for example) has more than 20?!

     

    I’ve designed a prototype board with an RF signal chain incorporated onto the pcb along with the AD9639. Using the LTC5585 demodulator along with Hittite HMC830LP6G LO. IF gain provided by LTC6409 operational amplifier. Signal path is operating perfectly. At the moment the signal chain is entirely depowered, and I’m just debugging the ADC. Also using an AD9510 clock dist IC, which accepts 200MHz (ABLJO crystal reference) and then divides down to 10MHz CMOS for (4x) LO PLL, the remaining LVPECL outputs being routed across an HmZd connector and to the ADC. The serial link is designed for about 60R single-ended impedance, 100R differential. Tracks are less than 20mm long to the connector.

     

    Capturing data with the HSC-ADC-EVALCZ (Altera version) and displaying with Visual Analog. When evaluating the ADC eval board, all works 100%. But on my prototype I see LSB toggles when selecting test data (MS short, +FS short, -FS short, checkerboard) outputs. There is no mention of how to enable the user-defined test patterns in the datasheet (register 0x0D).

     

    I realize that there are many potential pitfalls. Some of the things I’ve done so far:

    ·         Tried to eliminate clock dist IC by powering up ADC eval board, and jumping ADC clock and FPGA clock lines onto my prototype. Same issue.

    ·         Tried various output voltage options available on clock dist and ADC for serial stream. Same issue.

    ·         Lengthened clock lines to ADC and FPGA. Same issue.

    ·         Lengthened serial stream lines. Same issue.

     

    The next thing I’m going to do is jump the serial lines of the eval board onto my prototype board lines to check the integrity through the connector. Unfortunately I don’t have a 10GHz scope lying around to check eye diagrams. Only up to 1GHz. I might have access to a 8GHz scope though, if I ask nicely…

     

    Waveform below with 100kHz 200mVp-p waveform applied. Zoomed in on the right. The error is entirely repeatable across all channels at specific quanta.

     

    Appreciate all your efforts and help.

     

    Thanks

    Thomas

    attachments.zip
Reply
  • Hi Jonathan,

     

    As I understand it, the JESD204 standard only covers streams to 3.125GBps. How can the AD9639 then be compliant with JESD204 when it operates at a maximum of 4.2GBps?

     

    Can you confirm whether any other default registers not mentioned in the datasheet need to be set for correct operation? Why are there so few JESD registers for the AD9639 (1) when the AD9644 (for example) has more than 20?!

     

    I’ve designed a prototype board with an RF signal chain incorporated onto the pcb along with the AD9639. Using the LTC5585 demodulator along with Hittite HMC830LP6G LO. IF gain provided by LTC6409 operational amplifier. Signal path is operating perfectly. At the moment the signal chain is entirely depowered, and I’m just debugging the ADC. Also using an AD9510 clock dist IC, which accepts 200MHz (ABLJO crystal reference) and then divides down to 10MHz CMOS for (4x) LO PLL, the remaining LVPECL outputs being routed across an HmZd connector and to the ADC. The serial link is designed for about 60R single-ended impedance, 100R differential. Tracks are less than 20mm long to the connector.

     

    Capturing data with the HSC-ADC-EVALCZ (Altera version) and displaying with Visual Analog. When evaluating the ADC eval board, all works 100%. But on my prototype I see LSB toggles when selecting test data (MS short, +FS short, -FS short, checkerboard) outputs. There is no mention of how to enable the user-defined test patterns in the datasheet (register 0x0D).

     

    I realize that there are many potential pitfalls. Some of the things I’ve done so far:

    ·         Tried to eliminate clock dist IC by powering up ADC eval board, and jumping ADC clock and FPGA clock lines onto my prototype. Same issue.

    ·         Tried various output voltage options available on clock dist and ADC for serial stream. Same issue.

    ·         Lengthened clock lines to ADC and FPGA. Same issue.

    ·         Lengthened serial stream lines. Same issue.

     

    The next thing I’m going to do is jump the serial lines of the eval board onto my prototype board lines to check the integrity through the connector. Unfortunately I don’t have a 10GHz scope lying around to check eye diagrams. Only up to 1GHz. I might have access to a 8GHz scope though, if I ask nicely…

     

    Waveform below with 100kHz 200mVp-p waveform applied. Zoomed in on the right. The error is entirely repeatable across all channels at specific quanta.

     

    Appreciate all your efforts and help.

     

    Thanks

    Thomas

    attachments.zip
Children
No Data