Good morning (well, here anyway),
I'm having some issues with a JESD204 stream using an AD9639. The stream from the ADC eval board is working correctly. I've got a HSC-ADC-EVALCZ (Altera variant) capture board, and laid out my own prototype digital rx board. I'm using Visual Analog to capture streams and view data. The first thing I see is a bit toggle of the LSB when selecting test modes (MS short, +FS short, -FS short, checkerboard). All other bits in the 12-bit data are correct. The second issue I've noticed is erratic data when applying a none waveform at the input (a triangle was @ approximately 15kHz 700mVp-p, in this case). Images below.
I've been trying to debug possible clocking and physical hardware issues, but am getting more confident that there is no issue there. I've even jumped differential clock pairs from the ADC eval board across to my prototype to confirm that the clock distribution network (using an AD9510) isn't the issue. Behaviour is the same.
There are obviously plenty possible issues, but one other thing I'd like to confirm is that there are no potential issues with date of manufacture of the IC since it seems the JESD204 standard was evolving recently. Not sure if this is the date code, but the IC I've got on my prototype has #0938 (38th week of 2009) as code, with the eval board having #1103 (3rd week of 2011).
Thought I'd get the ball rolling here since I get no response from email@example.com.
Thanks in advance,