We have a radar system incorporating five AD12401 400MHz ADCs (now obsolete). We are unable to upgrade to the latest part at this time. There is a well known problem that the reset line does not fully reset all the internal registers for this ADC, so the interleaving of the two flash converters is ambiguous--this leads to synchronization problem, which are especially detrimental in coherent systems.
We are redoing the FPGA logic utilized in obtaining synchronization, (essentially iterative powering up the device until the desired state is achieved) but that work was done several years ago and needs updating to a less ad hoc and more reliable process.
Question: Upon application of reset to the AD12401, how can we unambiguously determine the obtained reset state, so we can (externally) swap the output samples to achieve the needed synchronization? A functional discussion or app note dealing with the underlying nature of the reset problem and its detection would be very helpful.
