To whom it may concern
I'm searching for a reference FPGA design of ad6645 and ad9764.
Is someone out there who has done such a design or can help me with this challange?
Yours with kind regards
Hi Mr. Larry -
Thank you for your quick reply.
A pseudo code is also enough for me .
Looking at the timing diagram of AD6644
The data can be captured when ENCODE is LOW and DRY is HIGH. Actually after 3 clock cycles the sampled data (N) is outputted.
DAC input data can be captured when CLOCK is high and IOUTA is high.
All the data outputs from the ADC and the DAC are available at the same time because of parallel output interfaces.
Here is my VHDL code for only ADC
if (RST_IN='1') then
dmout<=(others => '0');
elsif rising_edge(dry) then
leds<=fmin(13 downto 0); # ADC output to leds
elsif rising_edge(CLKFX_OUT) then
dmout <= (not(fmin) + "00000000000001");# DAC input
I wonder if my pseudo code or idea of data capturing is right or not .
Do I need to make any timing consideration about the set up or holding times of the converters and the FPGA in my VHDL code ?
Unfortunately for the AD6645, we do not have a reference design for FPGA capture code. This device is ~14 years old, I would suggest that you could move to a newer product, such as the AD9650, which uses a Virtex 4 FPGA as its data capture reference design. Let me know if you decide to move in that direction and we can help.
I have already spent ~800$ for the evaluation boards and now I want to use them. Unfortunately it will be hard to buy them for my masters thesis.
As I have stated in the above response to Mr. Larry all i want is a pseudo code that is needed for data capture and the things i need to be careful about when capturing data form ADc and feeding to DAC using an FPGA. It seems it will take a long time for me to understand and test .. That is why i could not finish my masters on time .
Please if you have any piece of code or any ideas about both ADC and DAC data capture steps let me know .
Any help i will appreciate.
Hi Mr. David,
Thank you very much for your mail, i will take a look at it.
I have made a parametric search about the converters :
It is seen that both AD6644-45 and AD9258 have parallel oputput data formats and they have pipelined ADC architectures. I thought that the output bits should be sampled at the same time. However in the AD9258 FPGA reference design the code is based on an SPI interface. Should the data be captured serially (bit by bit; thus I need 14 clock cycles at least) or can I have the data (all the 14 bits) at one clock cycle ?