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How to calculate the lock in time of internal PLL of CT ∑Δ ADC?

I was wondering if what should be the typical lock in time for PLL if it'd be integrated to CT ∑Δ? I've seen the datasheet of AD9261 but, it didn't contain any info about the locking time of PLL, but just the output frequency which is 640 MHz, and the input frequency which is 10MHz. Please help.

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