How to calculate the lock in time of internal PLL of CT ∑Δ ADC?

I was wondering if what should be the typical lock in time for PLL if it'd be integrated to CT ∑Δ? I've seen the datasheet of AD9261 but, it didn't contain any info about the locking time of PLL, but just the output frequency which is 640 MHz, and the input frequency which is 10MHz. Please help.

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    •  Analog Employees 
    on Mar 13, 2013 10:35 PM over 7 years ago

    Hello,

    If I understand your correctly, you intend on designing an external PLL circuit that generates the approximatley 640 MHz clock for the ADC (vs using its internal PLL clock syn). 

    If this is the case, you should wait for the external PLL to settle (10 usec) and then configure the AD9260 via SPI.    Note, the time it takes to configure the external PLL (also via SPI) and then start to configure the AD9260 is likely to take longer than 10 usec.

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  • 0
    •  Analog Employees 
    on Mar 13, 2013 10:35 PM over 7 years ago

    Hello,

    If I understand your correctly, you intend on designing an external PLL circuit that generates the approximatley 640 MHz clock for the ADC (vs using its internal PLL clock syn). 

    If this is the case, you should wait for the external PLL to settle (10 usec) and then configure the AD9260 via SPI.    Note, the time it takes to configure the external PLL (also via SPI) and then start to configure the AD9260 is likely to take longer than 10 usec.

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