High Speed ADC Consideration.

Hello All,

            A few queries about selecting the right ADC for our application, the requirements being the following:

1) Single channel

2) Measured results for Fin > 400MHz

3) Preferably serial LVDS output

Also a query regarding sub-sampling and over sampling.

1) Over sampling is a good thing because it spreads the quantization noise over a wider bandwidth, thereby decreasing the total noise in a smaller bandwidth.

2) Sub-sampling is affected by noise folding but can achieve the datasheet noise floor by using good band pass filters(BPF). My question is, how does one calculate the rejection requirement of the BPF (30dB, 40dB ... )?

In a subsampling system how does one evaluate the cumulative effect due to the increase in the quantization noise and also because of noise folding. Together they will give rise to a higher (much higher?) noise floor; is this avoidable? 

Regards,

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  • Hello David,

               Thank you for the answer. May I ask you to please also suggest parallel data out ADCs (CMOS, LVDS) with fin > 400MHz data; I found AD9445 but wish to know if there are others with measured results. We are considering both the options (parallel as we all as serial) as the power consumption for running the serial-LVDS at such a high clock rate might pose a limitation.

    Thanks again,

Reply
  • Hello David,

               Thank you for the answer. May I ask you to please also suggest parallel data out ADCs (CMOS, LVDS) with fin > 400MHz data; I found AD9445 but wish to know if there are others with measured results. We are considering both the options (parallel as we all as serial) as the power consumption for running the serial-LVDS at such a high clock rate might pose a limitation.

    Thanks again,

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