I'm using six AD9230 ADCs (clocked with 200MHz), all of them are connected to an FPGA. In order to synchronize the data to the FPGA internal clock I need to adjust some delay elements within the FPGA. Since the pn9 sequence is deterministic, it would be a nice way to perform the synchronization using the pseudo random numbers.
However, I'm wondering in which way the pn9 sequence is generated within the ADC. As stated in AN-877, the generator polynom is x^9+x^5+1. Is this realized with a 9-stage register, where the input is the modulo 2 addition of the first, the fifth and the ninth stage? If so, how do I get the 12 bits out of this register? I've checked the period of the sequence and it is 511=2^9-1 samples (12 bits per sample) which seems to be correct.
I'm using 2's complement data format and I'm unsure whether this has any impact on the respective bits.
It would be pretty nice if someone can explain the generation of the pn9 sequence and how it is influenced by the chosen data format.
Thanks in advance,