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# ad9653 pn9 and pn23 clarification

Hi,

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 - 1 or 511 bits. A descrip-

tion of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value

is all 1s (see Table 14 for the initial values). The output is a

parallel representation of the serial PN9 sequence in MSB-first

format. The first output word is the first 14 bits of the PN9

sequence in MSB aligned form.

Table 14. PN sequence specifies an initial value of 0x1FE0 for PN9.

I am confused if the PN9 shift register is 9 bit or 14 bit or something else?

In one pn9 implementation an initial value would be

loaded ie. 9'b111111111 and every 16 clock cycles a parallel word

is output, comprised from the msbit of the PN9 shift register from each clock cycle.

if (rst)

lfsr <= 9'b111111111;

else

lfsr <= {lfsr[7:0], lfsr[4] ^ lfsr[8]};

msb = lfsr[8];

For the PN23 the initial value matches the description and table 14.

Same confusion about the shift register size and which bits are taken

to form the 16 bit output?

Any help would be greatly appreciated.

Thanks Joe

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• Dear Joe,

And thank you for finding a typo in the AD9653 datasheet. Where it says, “The first output word is the first 14 bits . . .”, it should actually be “The first output word is the first 16 bits . . .” I apologize for the error. I have it marked for correction in the next revision.

Regarding your questions, the PN9 shift register is actually 16 bits. To advance the bit stream 16 times, all the bits need to be saved, thus necessitating a 16 bit shift register.

The PN23 shift register is 23 bits. It is advanced 16 times per ADC clock cycle to form the 16 bit output.

Does this give you what you need?

I hope your project goes well.

Sincerely,

Doug

• Dear Joe,

And thank you for finding a typo in the AD9653 datasheet. Where it says, “The first output word is the first 14 bits . . .”, it should actually be “The first output word is the first 16 bits . . .” I apologize for the error. I have it marked for correction in the next revision.

Regarding your questions, the PN9 shift register is actually 16 bits. To advance the bit stream 16 times, all the bits need to be saved, thus necessitating a 16 bit shift register.

The PN23 shift register is 23 bits. It is advanced 16 times per ADC clock cycle to form the 16 bit output.

Does this give you what you need?

I hope your project goes well.

Sincerely,

Doug

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