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# ad9653 pn9 and pn23 clarification

Hi,

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 - 1 or 511 bits. A descrip-

tion of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value

is all 1s (see Table 14 for the initial values). The output is a

parallel representation of the serial PN9 sequence in MSB-first

format. The first output word is the first 14 bits of the PN9

sequence in MSB aligned form.

Table 14. PN sequence specifies an initial value of 0x1FE0 for PN9.

I am confused if the PN9 shift register is 9 bit or 14 bit or something else?

In one pn9 implementation an initial value would be

loaded ie. 9'b111111111 and every 16 clock cycles a parallel word

is output, comprised from the msbit of the PN9 shift register from each clock cycle.

if (rst)

lfsr <= 9'b111111111;

else

lfsr <= {lfsr[7:0], lfsr[4] ^ lfsr[8]};

msb = lfsr[8];

For the PN23 the initial value matches the description and table 14.

Same confusion about the shift register size and which bits are taken

to form the 16 bit output?

Any help would be greatly appreciated.

Thanks Joe

• Dear Joe,

And thank you for finding a typo in the AD9653 datasheet. Where it says, “The first output word is the first 14 bits . . .”, it should actually be “The first output word is the first 16 bits . . .” I apologize for the error. I have it marked for correction in the next revision.

Regarding your questions, the PN9 shift register is actually 16 bits. To advance the bit stream 16 times, all the bits need to be saved, thus necessitating a 16 bit shift register.

The PN23 shift register is 23 bits. It is advanced 16 times per ADC clock cycle to form the 16 bit output.

Does this give you what you need?

I hope your project goes well.

Sincerely,

Doug

• Hi Doug,

Thank you for the response.

After a little bit of messing around i think i am OK for the PN9 sequence now.

A 9-bit PN9 shift register initialized with all ones and clocked 16 times for each output word

produces the attached values. First column is offset binary and second column is two complement.

These results do not match Table 14, initial and first three words for PN9.

The attached results match the output from the AD9653 (Test mode PN9 sequence).

Regards Joe

attachments.zip
• Hi Joe,

Thank you for closing the loop on this. Good work.

You are absolutely correct about the datasheet; I'll make sure it gets updated.

Doug

• In case it's helpful, here's a bit of C code that yields the PN9 sequence:

{

U16 acc = 0;

for (S32 i=0; i < ADC_bits; i++)

{

U8 Q4 = (*seed & (1 << 4)) != 0;

U8 Q8 = (*seed & (1 << 8)) != 0;

*seed = (*seed << 1) + (Q4 ^ Q8);

acc = (acc << 1) | Q8;

}

return (acc << (16-ADC_bits)) ^ 0x8000;

}

(Remove the trailing "^ 0x8000" subexpression to generate offset binary.)

This code works with the AD9253 but I've been having trouble modifying it to generate a matching PN23 sequence.  Can you elaborate on exactly what the data sheet means by "... the AD9253 inverts the bit stream with relation to the ITU standard"?

• Hi KE5FX,

Thank you for the PN9 code. The PN23 sequence generator is implemented the same way as the PN9, except that the output of the 18th and 23rd stages are XORed and fed back to the input stage.

I apologize for the wording related to PN23 inverting the bit stream with relation to the ITU standard. I believe this statement does not apply to the AD9253. I'll have this removed from the next datasheet revision.