AD9653 CLK+/CLK- 100MHz fundamental and harmonics on VIN+/-

Dear Sir/Madam,

The AD9653 in question has a 100MHz AC coupled LVPECL reference clock (CK+/CLK-) similar to Figure 64 in AD9653 Datasheet.

The main difference is the PECL driver manufacturer and termination resistors (150R to GND).

The IBIS and measured results match showing a 900mV common mode voltage and approx 1000mVpk-pk input at the AD9653.

The AD9653 is connect to a PGA from a different manufacturer. The 100MHz AD9653 reference clock fundamental and

harmonics can be observed on the AD9653 VIN+/- inputs / PGA outputs. The 100MHz fundamental and harmonics are not on

the PGA inputs, PGA power supply or even AD9653 power supply. Powering down the PGA has no affect. Powering down the AD9653

by writing to SPI register fixes the issue. The magnitude of the fundamental and harmonics are essentially the same when

measured on the CLK+/CLK- or VIN+/-. There is no coupling mechanism on the PCB.

Any thoughts would be welcome.

Regards Grant

  • Hi Grant,

    This is an interesting phenomenon.

    For clarification, you mentioned that a SPI power down fixes the issue. I assume that when the AD9653 is powered back up and is running, the issue is still fixed, correct?

    Thank you.


  • Hi Doug,

    Sorry when i meant SPI power down fixed the issue i meant that the clock was no longer observed on the AD9653 VIN+/- inputs. Powering the PGA and AD9653 down was done to try and locate the origin of the problem. So in summary when the AD9653 is powered and has a 100MHz clock, that clock is some how transferred to the VIN+/- inputs.

    Regards Grant

  • Hi Doug,

    The PGA is DC coupled to the AD9653 i.e no external filtering between PGA and ADC.

    Unfortunately, this is causing a big problem with sampling.

    Any chance we can talk offline?

    Regards Grant

  • Hi Grant,

    Yes, this is expected. The AD9653 is non-buffered and as such the inputs are to a switched capacitor circuit. What you are seeing is kick-back from the input circuit, which is toggled between sample and hold modes at the sample clock rate.

    The external filtering at the input (board level) serves to supress noise to the ADC, as well as to supress the kick-back.

    Do you have any filtering between the PGA and the ADC inputs? Is the kick-back causing problems in your application?



  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin