"High-Speed" ADC used for single-pulse conversion

Hi guys,

I am looking for a low cost ADC for a single conversion on an external trigger (ECL logic). The trigger comes exactly at the peak amplitude of the pulse (pulse-width < 20ns). I have found the AD9070 which is unfortunately an obsolete product. The digital outputs should be TTL (not ECL) but the conversion-start trigger should be ECL, otherwise (if using an ECL to TTL converter) the maximum amplitude is not hit anymore.

Input voltage range: 0 to 2.5V or 5V

no of bits: 10 or more

the speed of the ADC is not really important as we do not need to detect all pulses (only for monitoring purposes).

any suggestion is welcome!

thx

  • 0
    •  Analog Employees 
    on Jan 17, 2014 2:32 AM

    Hi,

    Unfortunately the AD9070 is obsolete.  But I'm not sure I follow your inquiry as the AD9070 had a 3 clock cycle latency between sampling the analog input and providing the  output data for that sample (see figure 1 page 3).  It sounds like you need a single clock cycle converter.  That would need to be a flash  or SAR architecture converter.   This post is in the high speed ADC  community, and we have not had a flash with low latency like you are seeking in many years.  Most of our high speed ADCs have migrated to a pipeline architecture for the ADC, and therefore have many clock cycles of latency as compared to the AD9070.  While I'm not an expert on our precision converter products, they do have some fast SAR architecture converters that might be low latency.  I would suggest that you consider posting an inquiry there and ask the same question. 

    Regards,

    David

  • Hi David,

    thx for the prompt answer!

    the clock cycle latency is not so important as far as I can see, but the timing of the sample&hold circuit, as it has to "freeze"/hold the amplitude value exatcly at the edge of my trigger (which is ECL). If the digital output is delayed this does not matter.

    Actually, due to the high speed S&H circuit, I have posted it in the High-Speed ADC section.

    best regards,

       Hannes

  • 0
    •  Analog Employees 
    on Jan 17, 2014 3:07 AM

    Hi,

    Even our pipeline ADCs have a S/H function at the front end to sample the input (I think this equates to your "freeze" term), and they are triggered by a differential sample clock input.  These inputs are typically not specified as  being logic family compatible, but a differential PECL signal is often used.  If 10 bits of resolution would be sufficient, then I would recommend looking at the AD9608. 

    www.analog.com/AD9608

    Regards,

    David