Post Go back to editing

AD927x: Standby mode and LVDS outputs

In the AD9272, AD9276, AD9278 and AD9279, it is written that:"During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed into a high impedance state."

Does this apply to the DCO and FCO outputs also?

Since I need to sample the data only about 10% of the time, I would like to put the AD927x in standby when not sampling to save on power consumption.

I want to interface it to an FPGA (spartan-6) so the deserialize the data, I need to connect the DCO to a PLL to generate the proper internal FPGA clock. If the FCO output is in high impedance state, the PLL will loose lock and screw up the timing! The PLL can take up to 100us to lock so this time adds to the 2us of power up of the AD927x.

Also, why is the standby power of the AD9278 and AD9279 twice as high as the AD9272 / AD9276, while the normal operating power is lower?

Parents
  • Hello Gym,

    The DCO and FCO outputs are not placed into high impedance mode during Standby mode.  They are kept running. 

    The difference in the Standby power between the AD9278/9 and the AD9272/6 is related to the behavior of the LNA during Standby.  To avoid a long recovery time for the AD9278/9 from Standby mode, the LNA is not powered down.  The AD9272/6 does not require the LNA to remain powered up to achieve quick recovery.

    Regards

    Gina

Reply
  • Hello Gym,

    The DCO and FCO outputs are not placed into high impedance mode during Standby mode.  They are kept running. 

    The difference in the Standby power between the AD9278/9 and the AD9272/6 is related to the behavior of the LNA during Standby.  To avoid a long recovery time for the AD9278/9 from Standby mode, the LNA is not powered down.  The AD9272/6 does not require the LNA to remain powered up to achieve quick recovery.

    Regards

    Gina

Children
No Data