AD9225 CLK stop and resume

 

Hi

I have some questions about AD9225.

This ADC does not have a PWDN terminal.

May I stop the clock of this device for a power save?  and how many cycles is it required for wake up?

I have tried bench test for wake up.

In order to acquire valid data, it was required 6 cycles.

Is additional wait time required for wake-up in addition to pipline delay( 3 cycles )?

best regards

wada

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  • 0
    •  Analog Employees 
    on Mar 18, 2014 5:59 PM

    Hello,

    The AD9225 is one of the 1st generation 12-bit CMOS ADC's released in the late 1990's.  As you state, it does not include a PWDN pin which exists on future generations of this product family.  No additional delay is required (other than pipeline delay you mention) since the VREF and bias circuitry remain enabled with clock stopped.  For a new design, you may want to consider a latter generation ADC like the AD9235 or AD9237 (which has PWDN function). 

    Regards.

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  • 0
    •  Analog Employees 
    on Mar 18, 2014 5:59 PM

    Hello,

    The AD9225 is one of the 1st generation 12-bit CMOS ADC's released in the late 1990's.  As you state, it does not include a PWDN pin which exists on future generations of this product family.  No additional delay is required (other than pipeline delay you mention) since the VREF and bias circuitry remain enabled with clock stopped.  For a new design, you may want to consider a latter generation ADC like the AD9235 or AD9237 (which has PWDN function). 

    Regards.

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