Questions about AD9257

Hello support team,

Please advice me about below questions related to AD9257.

1. I advised that Digital-reset(as shown below) after powerup in order to initialize a core of ADC.
   SPI_Write(0x08,0x03);#Digital Reset
   SPI_Write(0x08,0x00);#Normal Operation
   After the digital reset, it is required to delay  until normal operation and setting of register?

2. Soft reset is used for initialize of register, so isn't it need when powerup?

3. Have each digital data output phase gap? (ADC-A to ADC-H)
   If yes, how long shift?



  • Hello Tak-san,

    Thank you for considering the AD9257. Regarding your questions:

    1. After writing Register 0x08 = 0x03, you can write Register 0x08 = 0x00 as soon as the next clock cycle. Then after Register 0x08 is written with 0x00, the AD9257 will go through an initialization routine that takes about 3e6 (3 million) clock cycles. So, normal operation will start 3e6 clock cycles after Register 0x08 is written with 0x00. The outputs are not active during this time, so no data is available until the initialization is complete.
    2. Soft Reset does initialize the registers, but the registers are also initialized at power-up, so an additional Soft Reset should not be needed after power-up.
    3. If you are asking about input-to-output latency, there is a pipeline delay of 16 sample clock periods from input-to-output. If you are asking about phase differences between channels, all channels sample synchronously/simultaneously, so there is no phase difference between channels. There will of course be some small timing skew between channels due to mismatch, but there is no designed-in phase difference.

    Thank you again.