AD9266 digital output level

Evaluation board: AD9266-80EBZ.

Changes: I have changed the power so that DRVDD is 3.3V.

Problem: The signal level on the digital output is not going to GND. Here is a scope trace. CH1 (yellow) is the input signal. CH2 (blue) is D15/D14 (for this input signal the MSB is 1 on the peak and 0 in the trough) measured before RN808 and the buffer.

Is it normal for the output to sit at an indeterminate level like this? The datasheet doesn't mention anything about using a pull-down on the digital line, and I don't see one included in the evaluation board (apart from the PULLDOWN specified in the ucf file).

The output from Visual Analog (HSC-ADC-EVALCZ evaluation board) is attached below.

  • 0
    •  Analog Employees 
    on Oct 24, 2014 11:17 PM over 6 years ago

    Hi Jacques,

    What you are seeing is not normal. I tried to replicate your setup (AD9266-80EBZ, low frequency input tone, DRVDD = 3.3V) on my bench. Looking at the digital waveform at RN808 shows the signal swinging all the way down to ground. Also, you should see a nice reproduction of the input sine wave in the VisualAnalog Samples graph, but your picture obviously shows something different.

    It looks like your board ground might be noisy, but I do not have an explanation as to why. Are you powering the ADC board and FPGA board with the standard wall supplies?

    From your oscilloscope picture, it looks like your input tone is about 1.7MHz, 700mVpp single ended. Is this correct? From where in the circuit is the oscilloscope picture of the analog signal taken?

    I'll ask some of my colleagues if they have any additional ideas regarding this.



  • Doug,

    I am using the wall supplies that were supplied with the evaluation boards. Both have model number FY-0602000. The input tone is indeed ~1.7MHz, 700mVpp, so the scope trace is before the SMA connector INPUT A (J502).

    I think that you may be correct about the grounding. I will investigate this a bit more.

    If I implement the clock divider, the traces do improve: Here are some traces of the DCO line (no input connected - ignore the yellow trace). Ground is via the USB on the HSC-ADC-EVALCZ. The signal changes only marginally if the ground on the oscilloscope is attached to one of the GND posts (e.g. TP102).

    DCO, clock divide = 0x00

    DCO, clock divide = 0x01

    DCO, clock divide = 0x03

    DCO, clock divide = 0x07

  • 0
    •  Analog Employees 
    on Oct 28, 2014 12:01 AM over 6 years ago

    Hi Jacques,

    Thanks for sending the additional screenshots. This looks to be a different problem than reported in the first post. The screenshot in the first post shows data outputs (not DCO) having a noisy low level, as opposed to a slow slew rate. The new screenshots show DCO having a slow slew rate and not able to toggle when the clock divider is set to divide-by-1, and does not toggle rail-to-rail at divide-by-2.

    • If it is not too much trouble, can you try adjusting DCO drive strength with Register 0x15 to see if that makes any difference?
    • What was done on the board to change DRVDD to 3.3V?
    • Were any other modifications done to the board?

    Thank you.


  • Doug,

    Apologies for sending different traces. I had disconnected the input to remove the possibility of the input signal corrupting the ground. I meant to indicate the voltage levels, not the slew rate...

    (1) Setting 0x15 to 0xe2 or 0xa2 or 0x62 does not make any significant difference. There is a marginal increase in the Vpp, but not much.

    (2) I removed E105 and E107 (disconnect 1.8V regulators)

    I soldered across E108 (DUT_DRVDD == AUX_DVDD)

    I soldered across E109 and E111 (connect P102 & P103)

    I put a jumper between P102 pin 3 and P103 pin 1 (3.3V_AMPVDD == DUT_DRVDD)

    (3) I did modify it to send the input direct to the chip instead of going through the double balun input, but reverted that change when it did not help.


  • 0
    •  Analog Employees 
    on Oct 29, 2014 7:01 AM over 6 years ago

    Hi Jacques,

    Thanks for trying the drive strength adjustment. I should have mentioned this earlier; the different fields in Register 0x15 are enabled/disabled by Bit[7] in Register 0x14. For example, the default value of Register 0x14[7:0] = 0x00, which means that Register 0x14 Bit[7] = 0. This enables the 3.3V fields in Register 0x15, which are Bits[7:6] and Bits[3:2]. So for the Register 0x15 values of 0xE2, 0xA2 or 0x62, you should have seen some change in DCO, but no change in data.

    If by chance you used the non-default value of Register 0x14[7:0] = 0x80, then Register 0x14 Bit[7] = 1. This enables the 1.8V fields in Register 0x15, which are Bits[5:4] and Bits[1:0]. In this case, for the Register 0x15 values of 0xE2, 0xA2 or 0x62, you should have seen some a minor change in DCO, but again no change in data.

    Table 16 in the AD9266 datasheet shows these fields.

    Is Register 0x14 at default? Were you looking at DCO or data? Please let me know if the above needs more explanation.

    Your regulator modifications look to me like they should work, though in this scheme, U102 powers 3.3V_AMPVDD, DUT_DRVDD and AUX_DVDD, and U104 and U105 are unused.Please make sure you have a jumper on J503 between Pin 1 and Pin 2, to make sure that U501 is powered down. I don't expect that ADP1706 would have any trouble supplying current to these three domains, but you might want to check their voltages as a sanity check.

    If you are seeing any supply drop, perhaps a more direct way to do a similar thing, but shares the load, would be to:
    - Remove E105 (which you already did)

    - Leave E107 in place.
    - Solder across E108 (which you already did)
    - Leave everything else as it was before your modifications.

    This way DUT_DRVDD and AUX_DVDD are supplied by U105, and 3.3V_AMPVDD is supplied by U102

    In bypassing the baluns, did you remove them and jumper the traces, or wire around them? Regardless, the analog input network should not affect the output levels, unless somehow the grounds were affected.