Please help me!
I want to set AD9251 to interleaved output mode. all I need to do is set bit 5 of register "Output mode" (0x14)?
The Interleaved output mode is enabled globally onto both output channels via 0x14, bit 5. Here's a few more tips for using interleaved mode.
Since you typically won't need duplicated interleaved data on both CHA and CHB output ports, the undesired channel output can subsequently be disabled by selecting the desired Channel (A or B) Index at 0x05,
bits 1-0, then writing a 1 to local (channel specific) OEB register 0x14, bit 4.
The default order of interleaved (DDR) mode outputs CHA port data as ADC_A/B as shown in d/s
fig 3 and outputs CHB port data as ADC_B/A (not shown in d/s), although this can be reconfigured by
the customer to either A/B or B/A sequence using the “output Invert” bit 0x14, bit 2.
So in interleave mode (d/s fig 3) the respective A or B data is output for only ½ of the CLK period,
latched by both the rising and falling edges as opposed to the non-interleaved mode shown in fig 2.
Please let us know if you have any further questions about the AD9251 ADC family.
No, the Interleaved output mode (datasheet fig 3) is enabled automatically and globally onto both output channels via 0x14, bit 5. Register 0x2E is not typically needed for interleaved operation. Register 0x2E (Output assign) is typically used as a switch to route a desired single (non-interleaved) ADC input channel to a desired ADC output channel. By default ADC input channel A routes to ADC output A, and ADC input channel B routes to ADC output B. The default channel routing can be changed using Register 0x2E.