AD9650

Hi, I am wondering what is the current limit on the AIN inputs for the AD9650,

I am designing a high speed sampling system that has a +-10V peak pulse so I need dc coupled inputs.

Best Regards

Lasse Eriksson

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  • 0
    •  Analog Employees 
    on Dec 2, 2014 12:16 AM

    Hi Lasse,

    The AD9650 datasheet specifies an allowed voltage range for the input.  For normal operation, the AD9650 accepts a 0.9 V common mode voltage typically, but the common mode voltage can be increased as shown in Figure 67 of the datasheet to accommodate a 2.7 Vpp differential input.  To have a 2.7 Vpp differential input, each of the differential pins is allowed to swing 1.35V which is +/- 0.675 V. 

    So the max input is when the VIN+ pin = Vcm + 0.675; and the VIN- pin = Vcm - 0.675V.

    While the min signal is the VIN+ pin = Vcm - 0.675; and the VIN- pin = Vcm + 0.675V.

    Table 6 in the datasheet shows Maximum (not operating) range of the input pins to be -0.3 to AVDD + 0.2V.  Damage to the device will occur outside of this range.

    I'm not sure how you planned to accommodate the +/- 10V peak pulse, perhaps with a resistor divider network?

    Regards,

    Anthony

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  • 0
    •  Analog Employees 
    on Dec 2, 2014 12:16 AM

    Hi Lasse,

    The AD9650 datasheet specifies an allowed voltage range for the input.  For normal operation, the AD9650 accepts a 0.9 V common mode voltage typically, but the common mode voltage can be increased as shown in Figure 67 of the datasheet to accommodate a 2.7 Vpp differential input.  To have a 2.7 Vpp differential input, each of the differential pins is allowed to swing 1.35V which is +/- 0.675 V. 

    So the max input is when the VIN+ pin = Vcm + 0.675; and the VIN- pin = Vcm - 0.675V.

    While the min signal is the VIN+ pin = Vcm - 0.675; and the VIN- pin = Vcm + 0.675V.

    Table 6 in the datasheet shows Maximum (not operating) range of the input pins to be -0.3 to AVDD + 0.2V.  Damage to the device will occur outside of this range.

    I'm not sure how you planned to accommodate the +/- 10V peak pulse, perhaps with a resistor divider network?

    Regards,

    Anthony

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