AD9978A:How to use VDHDLATENCY_CTL?

Question

Hi all 
 How to use VDHDLATENCY_CTL? 
 Datasheet has not explain this register. 
 Could you please explain that register? 
 That register was described in AD9978A Sp０ Datasheet Page42　Table22 Address 0x5D： VDHDLATENCY_CTL. 
 BestRegards 
 aimPoint

TFAnalog · Accepted Answer

VDHDLATENCY_CTL register allows you to add a specified pipeline delay to the internal VD/HD signals. For example a setting of 1 will delay the internal VD/HD by 1 CLI cycle, setting of 2 will delay by 2 CLI cycles, etc..)

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AD9978A:How to use VDHDLATENCY_CTL?