Questions about AD9257

1) The data sheet is shown the effect of jitter of the input clock. (Page 22)

    Does this mean the effects of jitter of the rising edge?

2) Jitter of the falling edge of the input clock signal will affect the performance of the ADC?

   If it is correct, what are the effects?

3) Regard to the phase adjustment function of LVDS output clock:

    Shift of 180 ° means that tDATA is a quarter of the DCO frequency as shown in Figure2?

  • Hi Tak-san,

    1. Yes, the effect of jitter discussed on page 22 of the AD9257 datasheet is related to sampling, which on the AD9257 is at the rising edge.
    2. A jittery clock will probably have jitter on both rising and falling edges so of course in that case, SNR will be affected as in question 1 above. Jitter on the falling edge (non sampling edge) can also affect performance. Jitter specifically on the falling edge has the effect of modulating the time the ADC front end spends in the track phase of operation. This is the time before sampling when the input settles close-to-steady-state. This time-modulation from jitter on the non-sampling edge can cause errors due to incomplete settling, which again is manifested as noise and SNR degradation. The extent of this depends on the input settling of that particular board, and the sample rate (higher sample rates being more sensitive).
    3. Yes, the 180° as mentioned on page 25 of the AD9257 datasheet represents one half of a data-period, which is a quarter of a DCO cycle. This is a little confusing because one DCO cycle is defined as rise-to-rise (or equivalently fall-to-fall), while one data period (one bit width) is half of that, even though they can toggle at the same rate. The phase adjustments are approximate values. The main message is that the AD9257 output phase is adjustable.

    Thank you.

    Doug