AD9248 (HS ADC) --- Data Read

Hi ,

I am using AD9248 , High Speed ADC in my Design ....... I am interfacing it to the Spartan 6 FPGA.

I want to know ,when i have to read the the output parallel data.

There is input Clock  CLK_A for channel in A ... and  Output Enable OEB_A .

1. Will reading the output data be based on the input Clock CLK_A by giving the same clock to both ADC and FPGA , and OEB_A pulled      down to enable the O/P always ?

2, What if clock CLK_A for ADC is generated form FPGA itself ?

In Schematic i have connected input clock CLK_A to both ADC and FPGA , and OEB_A to GND.

Please reply...



HAL , Hyderabad

  • 0
    •  Analog Employees 
    on Mar 19, 2015 11:08 PM

    Hi Anoop,

    The optimum AD9248 performance is achieved when both ADC clocks (CLK_A and CLK_B) are operated at the same frequency and phase. This is ideally accomplished by tying the CLK_A and CLK_B inputs directly together and driving them from a common CLK source.

    1. Yes, tying the OutputEnable (OEB_A or OEB_B) low will permanently Enable the Digital Outputs for the respective Channel.

    2. Yes, the timing relationship between the Encode Clock and Data Outputs is reflected in datasheet fig 2. Additional ENCODE_CLK to DATAOUT delay timing flexibility is typically accomplished by adding additional delay buffers in the CLK path feeding the receiver/latches as detailed in the Evaluation board schematics/notes starting on datasheet page 22. Alternatively, such as in your case, this ENCODE_CLK to DATAOUT timing relationship can typically be adjusted within the FPGA itself.

    3. It is acceptable to CLK the AD9248 from the FPGA source but dynamic 14bit performance will be limited by any inherent jitter from a less than optimal CLK source as described in the "Clock Input and Considerations" section on datasheet pg 18.

    Best Regards,

    Tony M