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HSC-ADC-EVALCZ + AD9629-80EBZ + external trigger

Hello,

we recently purchased a combination of the HSC-ADC-EVALCZ and AD9629-80EBZ evaluation boards.

We would like to start the FIFO acquisition process by external trigger initiation.

Is there any way to make this setup work?

Best regards

Michael

  • Hi Michael,

    Thank you for evaluating the AD9629. I'm checking on the triggered capture capability of the FPGA program that runs on HSC-ADC-EVALCZ for the AD9629. I'll let you know after I have some information.

    This is a holiday weekend in the US so I, along with many of my colleagues, will be out of the office until Tuesday May 26. It will likely be after this that I'll be getting back to you.

    I apologize for the delay.

    Thanks,

    Doug

  • Hello again Michael,

    I have located an FPGA program file for AD9629 that has triggered capture capability. I'm still working with it on the bench to confirm its operation. I'll let you know after I have it working.

    Thanks,

    Doug

  • Hello Doug,

    thank you for your efforts. That sounds promising. I'm looking forward to testing it out soon.

    Thanks,

    Michael

  • Hi Michael,

    Here is the status. As far as I can tell, the FPGA code that allows for external trigger is working as intended, but it turns out that VisualAnalog (Analog Devices ADC evaluation software) needs to be modified to allow external trigger to work.

    I have requested the software group to make the modification to VisualAnalog. I do not know when they will be able to complete this, but I will let you know when it is ready. It might take a few weeks. Is this OK for you?

    I apologize for the delay. Thanks.

    Doug

  • Hi Doug,

    thank you for your fast response. That sounds very promising. The time window would also be OK as the matter at hand is not that time sensitive.

    Just for another clarificiation: Isn't it possible to trigger the sampling process externally and then manually read out the FIFO afterwards? That would be enough for our evaluation.

    Thanks,

    Michael

  • Hi Michael,

    Regarding your question about manually reading from the FIFO, the answer is almost-yes. The procedure that I will send you talks more about this, but you'll need to set a time interval (we call it the Fill Delay) after which the data will be read.

    Thanks,

    Doug

  • Hi Michael,


    I've put together some instructions on using the externally triggered capture feature on the AD9629 evaluation board and HSC-ADC-EVALCZ.

    Basically, to perform triggered capture, a new FPGA program needs to be loaded and the trigger signal is applied to SMA1 on HSC-ADC-EVALCZ after the voltage on SMA2 = 2.5V (ready signal).

    The details are contained in the QuickStart Guide. The following link contains the QuickStart guide and the FPGA program file.

    http://wiki.analog.com/_media/resources/eval/ad9649_9629_9609_triggered_capture_files.zip

    Contents:

    AD9649_29_09_TriggeredCapture_QuickStartGuide_PrA.pdf (Instructions)

    ad9649_fifo5.bin (FPGA program file)

    Please let me know if you have any questions. Thank you for using the AD9629.

    Doug

  • Hi Doug,

    We're using AD8283 board for our development test and I want to see if we can get the FPGA program file for using the external trigger data. I've seen FPGA files for other ADC boards but I could not find it for AD8283 board.

    is there any way to get that FPGA bin file?

    Thanks,

    Orod  

  • Hi Orod,

    I already reached out to the FPGA engr to send me the FPGA bin file.

    However, we could only send the file to you privately according to the engineer because he told us that it can't be posted here publicly. We'll send a follow-up email to you offline.

  • Hi Doug,

    I am working on a demo with an AD8285 ADC board connected to HSC-ADC-EVALCZ.

    I need to syncronize the acquisition with an external trigger. How can I set the FPGA registers for activate the reading of the external trigger on SMA connector?

    Thanks